# Soroush Abbaspour

## Soroush Abbaspour, Hopewell Junction, NY US

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20110041108 | MOMENT-BASED CHARACTERIZATION WAVEFORM FOR STATIC TIMING ANALYSIS - In one embodiment, the invention is a moment-based characterization waveform for static timing analysis. One embodiment of a method for mapping a timing waveform associated with a gate of an integrated circuit to a characterization waveform includes using a processor to perform steps including: computing one or more moments of the timing waveform and defining the characterization waveform in accordance with the moments. | 02-17-2011 |

## Soroush Abbaspour, Hopewill Jct., NY US

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20110016442 | Method of Performing Static Timing Analysis Considering Abstracted Cell's Interconnect Parasitics - An abstraction model supporting multiple hierarchical levels is inputted into a generalized static timing analysis of a hierarchical IC chip design to analyze and optimize the design of circuits integral to the chip containing a plurality of macro abstracts. An electrical network, synthesized for an internal abstract interconnect segment, is performed only once per macro and is applied to multiple instances of the macro abstract model in the IC chip design. The synthesized electrical network is a resistive capacitive or a resistive inductive capacitive network or a combination thereof. The synthesized electrical network is then used to match impulse response transfer functions of the network and the abstract interconnect segment's timing model. This network is stitched with the electrical parasitics of external interconnect segments connected to macro primary outputs. Various model order reductions are then performed on the electrical parasitics of external interconnects prior to network stitching. A static timing analysis is performed on the final network. | 01-20-2011 |

## Soroush Abbaspour, Hopewell Jct., NY US

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20100306723 | Order Independent Method of Performing Statistical N-Way Maximum/Minimum Operation for Non-Gaussian and Non-linear Distributions - A method and system to improve the performance of an integrated circuit (IC) chip by removing timing violations detected by performing a statistical timing analysis, given distributions of process and environmental sources of variation. The distributions are quantized using a minimum distortion criterion into discrete values. For each timing node of the IC circuit, a discrete minimum and maximum operation is performed on the timing parameters using a subset of combinations of the discrete values. The results of the discrete minimum and maximum operation are then de-quantized and propagated to a subsequent timing node and edge thereof. The process continues until one or more primary inputs and outputs of the IC chip are reached. The design of the IC chip is modified by removing all the timing violations identified. | 12-02-2010 |

## Soroush Abbaspour, Ossining, NY US

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20100115013 | EFFICIENT COMPRESSION AND HANDLING OF MODEL LIBRARY WAVEFORMS - A system and method for waveform compression includes preprocessing a collection of waveforms representing cell and/or interconnect response waveforms and constructing a representative waveform basis using linear algebra to create basis waveforms for a larger set of waveforms. The collection waveforms are represented as linear combination coefficients of an adaptive subset of the basis waveforms to compress an amount of stored information needed to reproduce the collection of waveforms. The representation of coefficients may be further compressed by, e.g., analytic representation. | 05-06-2010 |

20100269083 | Method of Employing Slew Dependent Pin Capacitances to Capture Interconnect Parasitics During Timing Abstraction of VLSI Circuits - A method for converting interconnect parasitics of an interconnect network into slew dependent pin capacitances utilizes charge matching between predetermined voltage thresholds. During timing abstraction of a macro, parasitics of interconnects connected to the primary inputs are represented as slew dependent pin capacitances in an abstract model being created. Interconnect model order reduction is employed to speed the process. The generated abstract is subsequently used in place of each occurrence of the macro during chip level hierarchical static timing analysis, leading to an enhanced accuracy of the timing analysis of the logic components driving the abstracts. | 10-21-2010 |

20110276933 | Method for Supporting Multiple Libraries Characterized at Different Process, Voltage, and Temperature Points - A method for accurately performing a timing, power, and noise analysis by pre-processing the characterization points of the available libraries, storing time consuming parts of the analysis and utilizing the pre-processed information during active runs to calculate the attributes at a desired PVT point. The PVT space is preferably sub-divided into triangular or rectangular regions, preferably obtained using Delaunay triangulation. In one embodiment, the invention performs an up-front pre-processing step on the characterized libraries to compute the static portion of the interpolation function that is independent of the specific instance; and a coefficient matrix that allows for interpolation of specific instances. | 11-10-2011 |

20120123725 | PERFORMING RELIABILITY ANALYSIS OF SIGNAL WIRES - A computer-implemented system, method, and storage device simulate a periodic voltage waveform in a network model of the integrated circuit design. The method then determines resultant current values in each segment of nets of the integrated circuit design resulting from the periodic voltage waveform and performs a Fourier transform of the periodic voltage waveform to generate a frequency domain representation of the periodic voltage waveform. The frequency domain representation comprises multiple Fourier terms, each of the Fourier terms is a frequency that is a multiple of the base frequency. Next, the method performs an AC analysis of the resultant voltage at each frequency of the multiple Fourier terms. The AC analysis provides an electrical current value for each of the frequencies of the Fourier terms for each of the nets. This allows the method to compute a root mean square current through each of the nets based on the AC analysis. Then, the method determines whether the root mean square current for any of the segments of the nets exceeds a current limit, and reports any segment of the nets for which the root mean square current exceeds the current limit. | 05-17-2012 |

20120124542 | Method and System for Optimizing a Device With Current Source Models - A method for optimizing a circuit includes at least a first branch and a second branch includes defining an objective function using a shape of waveforms measured at a timing point in each branch, and optimizing the objective function to minimize a variance of clock skew of the first branch and the second branch across different process voltage temperature values. | 05-17-2012 |

20120143582 | CHARACTERIZATION OF NONLINEAR CELL MACRO MODEL FOR TIMING ANALYSIS - A system, method and computer program product for modeling a semiconductor device structure. The system and method implemented includes performing a simulation of the circuit by applying at least one input waveform on a circuit input port, and loading an output port with at least one of output load; determining, at successive time steps of the circuit simulation, a voltage value Vi on the input port, a voltage value Vo on the output port, and a current values (ia) and (ib) on the respective input and output ports. Then there is computed from the respective current value for each successive time step of the simulation, at least one charge value (Qa(Vi, Vo)) and (Qb(Vi, Vo)), respectively, as a function of Vi and Vo voltage values; and generating a nonlinear charge source from the at least one charge value, the nonlinear charge source used in modeling a dynamic behavior of the cell. A voltage controlled charge source (VCCS) is thereby determined by capturing the natural digital circuit cell behavior. | 06-07-2012 |

20120245904 | WAVEFORM-BASED DIGITAL GATE MODELING FOR TIMING ANALYSIS - In one embodiment, the invention is a method and apparatus for waveform-based digital gate modeling for timing analysis. One embodiment of a method for modeling a gate of an integrated circuit chip includes building a transform matrix that indexes each input waveform/output waveform pair in a gate library to a plurality of different capacitive loads, obtaining an input waveform and a capacitive load associated with the gate, and, mapping the input waveform and the capacitive load to an output waveform for the gate, in accordance with the transform matrix. | 09-27-2012 |

## Soroush Abbaspour, Fishkill, NY US

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20080250370 | REPRESENTING AND PROPAGATING A VARIATIONAL VOLTAGE WAVEFORM IN STATISTICAL STATIC TIMING ANALYSIS OF DIGITAL CIRCUITS - An approach that represents and propagates a variational voltage waveform in statistical static timing analysis of digital circuits is described. In one embodiment, there is a statistical static timing analysis tool for analyzing digital circuit designs. The statistical static timing analysis tool includes a variational waveform modeling component that is configured to generate a variational waveform model that approximate arbitrary waveform transformations of waveforms at nodes of a digital circuit. The variational waveform model transforms a nominal waveform into a perturbed waveform in accordance with a plurality of waveform transformation operators that account for variations that occur between the nominal waveform and the perturbed waveform. A variational waveform propagating component is configured to propagate variational waveforms through a timing arc from at least one input to at least one output of the digital circuit in accordance with the variational waveform model. | 10-09-2008 |

20080270960 | METHOD FOR INCORPORATING MILLER CAPACITANCE EFFECTS IN DIGITAL CIRCUITS FOR AN ACCURATE TIMING ANALYSIS - A method for performing a static timing analysis on a circuit that includes gates and their respective interconnects by incorporating the effect of Miller capacitance on timing. A primitive gate is selected with its respective fan-out gates, interconnects attached to the primitive gate's output and interconnects attached to the output of each respective fan-out gate are determined. Using a metric, it is determined if the Miller capacitance effect of a CMOS gate on timing of its fan-out gate and interconnect timing is significant for each fan-out gate. If yes, the gate is replaced with a nonlinear driver model. If no, the gate is replaced with a fixed or dynamic capacitance. Next, if at least one of the fan-out gates is replaced with the nonlinear driver model, the primitive gate is likewise replaced with its corresponding nonlinear model as well. Then, a nonlinear timing simulation is performed on the circuit to generate voltage waveforms at the output of the primitive gate and the input of its fan-out gates that incorporate the effect of the Miller capacitance. However, if none of the fan-out gates are replaced with the nonlinear driver model, a conventional gate and interconnect timing analysis is preferably performed. | 10-30-2008 |

20090077515 | Method of Constrained Aggressor Set Selection for Crosstalk Induced Noise - A preliminary static timing analysis run is performed to calculate the delay and slew as well as timing windows for each net in the design, followed by coupling analysis for each given aggressor-victim combination, and to calculate the noise effect on the timing of victim net. Given a set of functional groups that relate the coupled aggressors to each other, the worst set of aggressors are calculated that satisfy the constraints from the functional groups, based on the calculated impact of each aggressor on the victim. Similarly the set of aggressors which contribute to the maximum amount of inductive coupling noise effect on timing are calculated. Furthermore, the coupling noise impact of the reduced set of aggressors on the given victim line and adjust the delay value calculated in the preliminary static timing analysis run. | 03-19-2009 |

20090193373 | MULTIPLE VOLTAGE THRESHOLD TIMING ANALYSIS FOR A DIGITAL INTEGRATED CIRCUIT - An approach for performing multiple voltage threshold timing analysis for a digital integrated circuit is described. In one embodiment, there is a multiple voltage threshold timing analysis tool for performing a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit. In this embodiment, a characterization data retrieving component is configured to obtain characterization data describing driving behavior of the at least one logic gate. An interconnect circuit model retrieving component is configured to obtain a model of the interconnect circuit. A multiple voltage threshold timing analysis component is configured to derive a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds. The multiple voltage threshold timing analysis component also generates a voltage waveform from the derived sequence of crossing times. | 07-30-2009 |