Patent application number | Description | Published |
20100035327 | Use of rice-derived products in a universal cell culture medium - The invention is used as an additive to a culture medium to maintain and grow various cells including stem cells and support their manufactured and secreted products including cytokines, chemokines and growth factors in an environment which provides: | 02-11-2010 |
20100284951 | Novel compositions for the treatment of wounds and skin care - The present invention provides novel compositions which comprise sodium hypochlorite, sodium, chloride, both organic and inorganic trace minerals in hypertonic condition presented in the forms of a clear aqueous solution (low or high concentrations for further reconstitution with purified water to obtain the final ready-to-use solution), gel or salve, lotion, wet pad, wet foam, ointment, stick, and dry mixture solution, for local application for the purposes of cleansing, disinfecting and inhibiting infection and promoting the natural healing of conditions such as fresh cuts, surgical stitches, chronic (diabetic gangrene) and acute wounds, herpes zoster, athlete's foot, and bed sores, without the necessity for covering up the wounds with gauzes/plasters nor any concurrent use of topical medication. These compositions are also suitable for the treatment of conditions such as unpleasant body odor, acne and mixed bacterial infection in the ear. | 11-11-2010 |
Patent application number | Description | Published |
20080299756 | METHOD AND APPARATUS FOR PLATING A SEMICONDUCTOR PACKAGE - A method of plating a plurality of semiconductor devices includes: applying an electrical power source to an anode terminal and a cathode terminal; placing the plurality of semiconductor devices on a non-conductive platform in a plating solution; moving conductive parts across surfaces of the semiconductor devices to be plated, wherein the conductive parts electrically connect the surfaces of the semiconductor devices to the cathode; and wherein plating particles connected to the anode terminal move to and plate the surfaces of the semiconductor devices. | 12-04-2008 |
20100127363 | Very extremely thin semiconductor package - A package and method of making thereof. The package includes a first plated area, a second plated area, a die, a bond, and a molding. The die is attached to the first plated area, and the bond couples the die to the first and/or the second plated areas. The molding encapsulates the die, the bonding wire, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. | 05-27-2010 |
20100140081 | Method and apparatus for plating a semiconductor package - A method of plating a plurality of semiconductor devices includes: applying an electrical power source to an anode terminal and a cathode terminal; placing the plurality of semiconductor devices on a non-conductive platform in a plating solution; moving conductive parts across surfaces of the semiconductor devices to be plated, wherein the conductive parts electrically connect the surfaces of the semiconductor devices to the cathode; and wherein plating particles connected to the anode terminal move to and plate the surfaces of the semiconductor devices. | 06-10-2010 |
20100311208 | METHOD AND APPARATUS FOR NO LEAD SEMICONDUCTOR PACKAGE - A leadframe for use in fabricating a no lead semiconductor package contains connecting bars between individual electrical contact pads. For embodiments having a die pad, the leadframe further includes connecting bars between the contact pads and the die pad. The lower surfaces of the connecting bars are coplanar with the lower surfaces of the contact pads and/or the die pad, and the upper surfaces of the connecting bars are recessed with respect to the upper surfaces of the contact pads and/or the die pad. The semiconductor package is fabricated by encapsulating the die and the leadframe in a molding compound and then removing the connecting bars. The leadframe is typically formed by half etching a metal sheet to form the connecting bars. The connecting bars are removed from the encapsulated package by a selected cutting, sawing, or etching means, based on a predetermined pattern. | 12-09-2010 |
20100327432 | PACKAGE WITH HEAT TRANSFER - A semiconductor package includes an encapsulant, a semiconductor device within the encapsulant, and one or more terminals for electrically coupling the semiconductor device to a node exterior to the package. The package further includes bonding means coupling the semiconductor device to the one or more terminals. The semiconductor package is configured to dissipate heat through a top surface of the package. To directly dissipate heat via the top surface of the package, a thermally conductive layer is coupled to the semiconductor device, and the layer is exposed at a surface of the package. | 12-30-2010 |
20110039371 | FLIP CHIP CAVITY PACKAGE - A process for forming a semiconductor package. The process comprises forming a first leadframe strip mounted upon an adhesive tape. The first leadframe strip is at least partially encased in a first mold compound thereby forming a molded leadframe strip. At least one flip chip semiconductor device is mounted on the molded leadframe strip. The semiconductor device has conductive masses attached thereon to effectuate electrical contact between the semiconductor device and the molded leadframe. The conductive masses can be substantially spherical or cylindrical. Liquid encapsulant is dispensed on the semiconductor device to encapsulate the flip chip semiconductor device. A cavity is formed between the semiconductor device and the molded leadframe. The molded leadframe strip, the semiconductor device, and the conductive masses are at least partially encased in a second mold compound. The second mold compound can be molded so that a surface of the flip chip semiconductor device that is not attached to the molded leadframe is substantially exposed or molded to produce a globular form on the flip chip semiconductor device. The molded leadframe strip is singulated to form discrete semiconductor packages. | 02-17-2011 |
20110076805 | MOLDED LEADFRAME SUBSTRATE SEMICONDUCTOR PACKAGE - A process for forming land grid array semiconductor packages includes a leadframe that is supported by a substrate comprising mold compound. In some embodiments, at least one die is electrically coupled to the leadframe by bondwires. The package comprises a second mold compound to act as an encapsulant. An apparatus for forming a land grid array semiconductor package includes means for molding a leadframe, assembling thereon at least one semiconductor device, applying a second mold, and singulating to form individual devices. A land grid array package comprises a leadframe, a substrate for supporting the leadframe, at least one semiconductor device and a mold compound. | 03-31-2011 |
20110147931 | LEAD FRAME LAND GRID ARRAY WITH ROUTING CONNECTOR TRACE UNDER UNIT - A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package. | 06-23-2011 |
20110198752 | LEAD FRAME BALL GRID ARRAY WITH TRACES UNDER DIE - A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package. | 08-18-2011 |
20120066899 | QFN PROCESS FOR STRIP TEST - A process for assembling semiconductor devices comprises encapsulating a leadframe matrix having semiconductor die mounted thereon in a mold compound. The leadframe matrix is partially singulated to electrically isolate each individual leadframe unit. A plurality of leadframe units is tested simultaneously. The leadframe matrix is completely singulated. Non compliant units are discarded. | 03-22-2012 |
20130243893 | MOLDED LEADFRAME SUBSTRATE SEMICONDUCTOR PACKAGE - A process for forming land grid array semiconductor packages includes a leadframe that is supported by a substrate comprising mold compound. In some embodiments, at least one die is electrically coupled to the leadframe by bondwires. The package comprises a second mold compound to act as an encapsulant. An apparatus for forming a land grid array semiconductor package includes means for molding a leadframe, assembling thereon at least one semiconductor device, applying a second mold, and singulating to form individual devices. A land grid array package comprises a leadframe, a substrate for supporting the leadframe, at least one semiconductor device and a mold compound. | 09-19-2013 |
20130280866 | LEAD FRAME BALL GRID ARRAY WITH TRACES UNDER DIE - A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package. | 10-24-2013 |
20130337609 | LEAD FRAME LAND GRID ARRAY WITH ROUTING CONNECTOR TRACE UNDER UNIT - A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package. | 12-19-2013 |
20140015117 | VERY EXTREMELY THIN SEMICONDUCTOR PACKAGE - A package and method of making thereof. The package includes a first plated area, a second plated area, a die, a bond, and a molding. The die is attached to the first plated area, and the bond couples the die to the first and/or the second plated areas. The molding encapsulates the die, the bonding wire, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. | 01-16-2014 |