Patent application number | Description | Published |
20130069622 | ELECTRON RADIATION MONITORING SYSTEM TO PREVENT GOLD SPITTING AND RESIST CROSS-LINKING DURING EVAPORATION - Disclosed herein are systems and methods for in-situ measurement of impurities on metal slugs utilized in electron-beam metal evaporation/deposition systems, and for increasing the production yield of a semiconductor manufacturing processes utilizing electron-beam metal evaporation/deposition systems. A voltage and/or a current level on an electrode disposed in a deposition chamber of an electron-beam metal evaporation/deposition system is monitored and used to measure contamination of the metal slug. Should the voltage or current reach a certain level, to the deposition is completed and the system is inspected for contamination. | 03-21-2013 |
20130078928 | APPARATUS AND METHODS FOR FIXED DC BIAS TO IMPROVE LINEARITY IN SIGNAL PROCESSING CIRCUITS - To maintain linear operation of a signal processing circuit, such as a low noise amplifier, a peak detector detects a peak of a signal associated with the signal processing circuit and compares the detected peak signal with a threshold. When the detected peak signal is greater than the threshold, a fixed current source biases the signal processing circuit to place the signal processing circuit in a different mode of operation. The signal processing circuit may thereby process a larger input signal while operating in an acceptable linear region. | 03-28-2013 |
20130078929 | APPARATUS AND METHODS FOR VARIABLE DC BIAS TO IMPROVE LINEARITY IN SIGNAL PROCESSING CIRCUITS - To maintain linear operation of a signal processing circuit, such as a low noise amplifier, a peak detector detects a peak of a signal associated with the signal processing circuit and compares the detected peak signal with a threshold. When the detected peak signal is greater than the threshold, a variable current source biases the signal processing circuit to place the signal processing circuit in a different mode of operation. The signal processing circuit may thereby process a larger input signal while operating in an acceptable linear region. | 03-28-2013 |
20130090077 | GAIN CONTROL SYSTEMS AND METHODS FOR CONTROLLING AN ADJUSTABLE POWER LEVEL - A system, such as a transceiver, for controlling an adjustable power level includes first and second power detectors, a network of attenuators, a compensator, a comparator, and a controller. The first power detector measures the power of a signal. The network of attenuators receives the signal and generates an attenuated signal. The compensator receives the attenuated signal and generates a compensated signal. The second power detector measures the power of the compensated signal. The comparator receives the respective outputs from the first and second power detectors and generates a first error signal. The controller enables the fixed attenuation, correspondingly adjusts the variable attenuation, receives a second error signal, and provides a control signal to the network of attenuators to nullify an attenuation mismatch introduced between the fixed attenuation and the variable attenuation. A corresponding method for controlling an adjustable power level is also disclosed. | 04-11-2013 |
20130100993 | DUAL MODE POWER AMPLIFIER CONTROL INTERFACE WITH A THREE-MODE GENERAL PURPOSE INPUT/OUTPUT INTERFACE - In accordance with some embodiments, the present disclosure relates to a dual mode control interface that can be used to provide both a radio frequency front end (RFFE) serial interface and a three-mode general purpose input/output (GPIO) interface within a single digital control interface die. In certain embodiments, the dual mode control interface, or digital control interface, can communicate with a power amplifier. Further, the dual mode control interface can be used to set the mode of the power amplifier. | 04-25-2013 |
20130115895 | DEVICES AND METHODS RELATED TO FIELD-EFFECT TRANSISTOR STRUCTURES FOR RADIO-FREQUENCY APPLICATIONS - Disclosed are devices and methods related to field-effect transistor (FET) structures configured to provide reduced per-area values of resistance in the linear operating region (Rds-on). Typical FET devices such as silicon-on-insulator (SOI) device require larger device sizes to desirably lower the Rds-on values. However, such increases in size result in undesirably larger die sizes. Disclosed are various examples of shapes of source, drain, and corresponding gate that yield reduced Rds-on values without having to increase the device size. In some implementations, such FET devices can be utilized in high power radio-frequency (RF) switching applications. | 05-09-2013 |
20130116017 | APPARATUS AND METHODS FOR POWER AMPLIFIERS - Apparatus and methods for power amplifiers are disclosed. In one embodiment, a power amplifier circuit assembly includes a power amplifier and an impedance matching network. The impedance matching network is operatively associated with the power amplifier and is configured to provide a load line impedance to the power amplifier between about 6 Ω and about 10 Ω. The impedance matching network includes a fundamental matching circuit and one or more termination circuits, and the fundamental matching circuit and each of the of the one or more termination circuits include separate input terminals for coupling to an output of the power amplifier so as to allow the fundamental matching circuit and each of the one or more termination circuits to be separately tuned. | 05-09-2013 |
20130119535 | FLIP CHIP PACKAGES WITH IMPROVED THERMAL PERFORMANCE - Systems and methods for improving thermal performance, such as thermal dissipation, of flip chip packages that include one or more flip chip dies are disclosed. In some embodiments, a thermal collection layer can be formed on a surface of a flip chip die. The thermal collection layer can be configured to dissipate heat generated by the flip chip die. In some variations, the thermal collection layer can be constructed using materials having high thermal conductivity. | 05-16-2013 |
20130127548 | APPARATUS AND METHODS FOR VOLTAGE CONVERTERS - Apparatus and methods for voltage converters are provided. In one embodiment, a voltage conversion system includes a bypass circuit and a voltage converter including an inductor and a plurality of switches configured to control a current through the inductor. The bypass circuit includes a first p-type field effect transistor (PFET), a second PFET, a first n-type field effect transistor (NFET), and a second NFET. The first and second NFET transistors and the first and second PFET transistors are electrically connected between a first end and a second end of the inductor such that a source of the first PFET transistor and a drain of the first NFET transistor are electrically connected to the first end of the inductor and such that a drain of the second PFET transistor and a source of the second NFET transistor are electrically connected to the second end of the inductor. | 05-23-2013 |
20130130630 | RADIO-FREQUENCY SWITCHES HAVING SILICON-ON-INSULATOR FIELD-EFFECT TRANSISTORS WITH REDUCED LINEAR REGION RESISTANCE - Disclosed are devices and methods related to radio-frequency (RF) switches having silicon-on-insulator (SOI) field-effect transistors (FETs). In some embodiments, an RF switch can include an FET with shaped source, drain, and gate selected to yield a reduced per-area value of resistance in linear operating region (Rds-on). In some implementations, a plurality of such FETs can be connected in series to allow use of SOI technology in high power RF switching applications while maintaining a relatively small die size. | 05-23-2013 |
20130130750 | MULTI-MODE POWER AMPLIFIER - A multi-mode power amplifier includes a high-power mode amplifier circuit, a mid-power mode amplifier circuit, and a low power amplifier circuit, where the low-power mode amplifier circuit comprises a plurality of independently selectable power cell/amplifier branches. The multi-mode power amplifiers selectively enable or disable amplifier branches to provide multiple levels of amplification. Selectively enabling certain of a plurality of split collector amplifier branches provides multiple low power and ultra-low power amplifier modes without the impedance mismatch or board layout problems associated with an RF switch. | 05-23-2013 |
20130130752 | FLIP-CHIP LINEAR POWER AMPLIFIER WITH HIGH POWER ADDED EFFICIENCY - Disclosed are devices and methods for improving power added efficiency and linearity of radio-frequency power amplifiers implemented in flip-chip configurations. In some embodiments, a harmonic termination circuit can be provided so as to be separate from an output matching network configured to provide impedance matching at a fundamental frequency. The harmonic termination circuit can be configured to terminate at a phase corresponding to a harmonic frequency of the power amplifier output. Such a configuration of separate fundamental matching network and harmonic termination circuit allows each to be tuned separately to thereby improve performance parameters such as power added efficiency and linearity. | 05-23-2013 |
20130135025 | DUAL MODE POWER AMPLIFIER CONTROL INTERFACE WITH A TWO-MODE GENERAL PURPOSE INPUT/OUTPUT INTERFACE - In accordance with some embodiments, the present disclosure relates to a dual mode control interface that can be used to provide both a radio frequency front end (RFFE) serial interface and a two-mode general purpose input/output (GPIO) interface within a single digital control interface die. In certain embodiments, the dual mode control interface, or digital control interface, can communicate with a power amplifier. Further, the dual mode control interface can be used to set the mode of the power amplifier. | 05-30-2013 |
20130137199 | SYSTEMS AND METHODS FOR MONITORING HETEROJUNCTION BIPOLAR TRANSISTOR PROCESSES - Disclosed are systems and methods related to monitoring of heterojunction bipolar transistor (HBT) processes. In some embodiments, a capacitance element can be fabricated during an HBT process by forming an emitter layer having material such as indium gallium phosphide (InGaP) over a gallium arsenide (GaAs) base layer, forming a barrier layer such as a tantalum nitride (TaN) layer over the emitter layer, and forming a metal layer over the barrier layer. Aside from the metallization of the emitter, the resulting capacitance element has a capacitance value representative of the thickness of the emitter layer. Accordingly, monitoring of such a capacitance value during various HBT processes allows monitoring of the integrity of the emitter layer. | 05-30-2013 |
20130137382 | DEVICES AND METHODS RELATED TO A BARRIER FOR METALLIZATION OF A GALLIUM BASED SEMICONDUCTOR - Disclosed are structures and methods related to a barrier layer for metallization of a selected semiconductor such as indium gallium phosphide (InGaP). In some embodiments, the barrier layer can include tantalum nitride (TaN). Such a barrier layer can provide desirable features such as barrier functionality, improved adhesion of a metal layer, reduced diffusion, reduced reactivity between the metal and InGaP, and stability during the fabrication process. In some embodiments, structures formed in such a manner can be configured as an emitter of a gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) or an on-die high-value capacitance element. | 05-30-2013 |
20130143411 | SYSTEMS AND METHODS FOR IMPROVING FRONT-SIDE PROCESS UNIFORMITY BY BACK-SIDE METALLIZATION - Disclosed are systems and methods for improving front-side process uniformity by back-side metallization. In some implementations, a metal layer can be formed on the back side of a semiconductor wafer prior to certain process steps such as plasma-based processes. Presence of such a back-side metal layer reduces variations in, for example, thickness of a deposited and/or etched layer resulting from the plasma-based processes. Such reduction in thickness variations can result from reduced variation in radio-frequency (RF) coupling during the plasma-based processes. Various examples of wafer types, back-side metal layer configurations, and plasma-based processes are disclosed. | 06-06-2013 |
20130157594 | CIRCUITS AND METHODS FOR INCREASING OUTPUT FREQUENCY OF AN LC OSCILLATOR - Disclosed are circuits and methods for increasing an output frequency of an inductance-capacitance (LC) oscillator. In some embodiments, the LC oscillator can be implemented as a voltage-controlled oscillator (VCO) having differential outputs. When the VCO is implemented on a die, wirebond connections from the outputs to a ground results in an effective inductance that impacts a maximum frequency associated with the VCO. An electrical connection such as a wirebond between the differential outputs yields a reduction in the effective inductance thereby increasing the maximum frequency. In some embodiments, the wirebond between the differential outputs can be configured so that its contribution to mutual inductance is reduced or substantially nil. | 06-20-2013 |
20130194158 | DEVICES AND METHODS RELATED TO ELECTROSTATIC DISCHARGE-PROTECTED CMOS SWITCHES - Disclosed are devices and methods related to a CMOS switch for radio-frequency (RF) applications. In some embodiments, the switch can be configured to include a resistive body-floating circuit to provide improved power handling capability. The switch can further include an electrostatic discharge (ESD) protection circuit disposed relative to the switch to provide ESD protection for the switch. Such a switch can be implemented for different switching applications in wireless devices such as cell phones, including band-selection switching and transmit/receive switching. | 08-01-2013 |