Patent application number | Description | Published |
20130064020 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a first data input/output line configured to transmit data from a first memory bank; a second data input/output line configured to transmit the data from the first memory bank; a first data output section configured to align and output data transmitted through the first data input/output line based on an input/output mode; and a second data output section configured to align and output either data transmitted through the first input/output line or the second data input/output line based on the input/output mode and an address signal. | 03-14-2013 |
20130077377 | SEMICONDUCTOR DEVICE WITH OTP MEMORY CELL - A semiconductor device includes a one-time programmable (OTP) memory cell includes a first MOS transistor having a gate coupled to a bit line, a first switching device, coupled to one side of a source/drain of the first MOS transistor, configured to provide a current path for a current supplied to the gate of the first MOS transistor, and a second switching device configured to provide a bias voltage at the other side of the source/drain of the first MOS transistor. | 03-28-2013 |
20130077861 | IMAGE SENSING DEVICE AND IMAGE DATA PROCESSING METHOD USING THE SAME - An image data processing method includes generating a data window comprising N rows and N columns using Bayer data from a pixel array, generating a red (R), green (G), blue (B) data of a center pixel in the data window, detecting an edge region in the data window, detecting a bright region in the data window, adjusting the R, G, B data using a suppressing gain factor if both of the edge region and bright region is detected, and outputting the adjusting R, G, B data as a result of an interpolating process. | 03-28-2013 |
20130088930 | NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device includes a page buffer unit configured to include a plurality of page buffers coupled to the respective bit lines; a pass/fail circuit coupled to the page buffer unit and configured to perform a pass/fail check operation by comparing the amount of current, varying according to verify data stored in the plurality of page buffers, with an amount of reference current corresponding to the number of allowed error correction code bits; and a masking circuit configured to preclude the pass/fail check operation by coupling a ground terminal to sense nodes coupled to the remaining page buffers, respectively, other than page buffers corresponding to column addresses having the identical upper bits as an input column address. | 04-11-2013 |
20130114359 | INPUT/OUTPUT CIRCUIT AND METHOD OF SEMICONDUCTOR APPARATUS AND SYSTEM WITH THE SAME - A system includes a controller which is capable of operating at one of a first speed and a second speed slower than the first speed; a semiconductor memory apparatus operating at the first speed; and an input/output device which is connected between the semiconductor memory apparatus and the controller, and configured to control input/output of signals between the controller and the semiconductor memory apparatus, wherein the input/output device operates in a normal mode which corresponds to the input/output of the signals between the controller operating at the first speed and the semiconductor memory apparatus and a test mode which corresponds to the input/output of the signals between the controller operating at the second speed and the semiconductor memory apparatus. | 05-09-2013 |
20130126956 | SEMICONDUCTOR DEVICE INCLUDING VERTICAL TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a vertical transistor and a method for manufacturing the same may reduce a cell area in comparison with a conventional layout of 8F2 and 6F2. Also, the method does not require forming a bit line contact, a storage node contact or a landing plug, thereby decreasing the process steps. The semiconductor device including a vertical transistor comprises: an active region formed in a semiconductor substrate; a bit line disposed in the lower portion of the active region; a word line buried in the active region; and a capacitor to disposed over the upper portion of the active region and the word line, | 05-23-2013 |
20130126962 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are provided. After spacers are formed on sidewalls of a pillar pattern and a photoresist pattern exposing an OSC formation region is formed on a semiconductor substrate including the pillar pattern and the spacer, processes for removing a spacer corresponding to the OSC formation region to form an OSC, removing the photoresist pattern, forming a bit line between the pillar patterns, an epitaxial layer on the pillar pattern, and forming a vertical gate and a storage node contact, are performed so that the OSC formation process can be simplified. In addition, the OSC formation process is performed in a state that the pillar pattern has a low height so that a failure such as a not-open failure caused in the OSC formation process can be prevented. | 05-23-2013 |
20130126964 | SEMICONDUCTOR DEVICE INCLUDING VERTICAL TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a vertical transistor and a method for forming the same are disclosed, which can greatly reduce a cell area as compared to a conventional layout of 8F2 and 6F2, and need not form a bit line contact, a storage node contact, or a land plug, such that the number of fabrication steps is reduced and a contact region between the bit line and the active region is increased in size. The semiconductor device including a vertical transistor includes an active region formed over a semiconductor substrate, a first recess formed to have a predetermined depth at both sides of the active region, and a bit line buried in the first recess. | 05-23-2013 |
20130127013 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor device, a support wall is formed between storage nodes to more effectively prevent leaning of a capacitor, and the storage nodes are formed using a damascene process, which may increase a contact area between each storage node and a storage node contact. | 05-23-2013 |
20130134374 | VARIABLE RESISTOR, NON-VOLATILE MEMORY DEVICE USING THE SAME, AND METHODS OF FABRICATING THE SAME - A variable resistor, a nonvolatile memory device and methods of fabricating the same are provided. The variable resistor includes an anode electrode and a cathode electrode, a variable resistive layer including CdS nanoscale particles provided between the anode electrode and the cathode electrode, and an initial metal atom diffusion layer within the variable resistive layer. The variable resistor is a bipolar switching element and configured to be in a reset state when a positive voltage relative to a cathode electrode is applied to the anode electrode, and configured to be in a set state when a negative voltage relative to the cathode electrode is applied to the anode electrode. | 05-30-2013 |
20130141144 | POWER-UP SIGNAL GENERATION CIRCUIT - A power-up signal generation circuit includes: a first section signal generation unit configured to sense a level of an external voltage and a level of an internal voltage and generate a first section signal; a second section signal generation unit configured to output a second section signal by buffering the first section signal when the internal voltage is lowered to below a minimum level; and a selective output unit configured to output the first section signal as a power-up signal, wherein the selective output unit outputs the second section signal as the power-up signal when a power-up section is ended and a mode register setting operation is performed. | 06-06-2013 |
20130141975 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME - A semiconductor memory device capable of reducing the size of a NAND flash memory device includes a latch unit configured to store a bad block address, a comparator configured to compare the bad block address with an access address so as to output a bad-block detection signal, and a bad block controller configured to sequentially output a plurality of bad block pulses corresponding to the bad-block detection signal during a predetermined period in response to a plurality of bad-block flag signals that are sequentially activated. | 06-06-2013 |
20130141982 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a memory array including a plurality of memory cells, and a peripheral circuit configured to perform an erase operation by supplying a first erase voltage to selected memory cells and perform an erase verify operation by supplying an erase verify voltage to the selected memory cells, wherein the peripheral circuit is configured to increase the first erase voltage to a first level at a first rising rate for a first rising period and increase the first erase voltage to a first target level at a second rising rate lower than the first rising rate for a second rising period. | 06-06-2013 |
20130147995 | SIGNAL PROVIDING APPARATUS, AND ANALOG-TO-DIGITAL CONVERTING APPARATUS AND IMAGE SENSOR USING THE SAME - An image sensor includes: a plurality of image pixels providing a reset signal and a data signal; a signal providing apparatus generating a ramp signal, and sequentially providing the reset signal, the data signal, and the ramp signal; and an analog-to-digital converting apparatus converting the data signal into a digital signal by using a first timing at which the amplitude of the ramp signal is changed based on the amplitude of the reset signal and a second timing at which the amplitude of the ramp signal is changed based on the amplitude of the data signal, wherein the reset signal used to generate the ramp signal and the data signal which has been converted into the data digital signal may be output from the same image pixel. | 06-13-2013 |
20130148433 | OPERATING METHOD IN A NON-VOLATILE MEMORY DEVICE - A method of verifying a non-volatile memory device includes precharging a bit line to a high level through a sensing node by applying a first voltage to a bit line select transistor coupled between the bit line and the sensing node; applying a verifying voltage to a plurality of word lines; disconnecting the bit line from the sensing node; and coupling the bit line to the sensing node by applying a second voltage to the bit line select transistor so as to detect a level of the bit line, the second voltage being smaller than the first voltage, wherein, a difference between the first voltage and the second voltage in a verifying operation is higher than a difference between a first voltage and a second voltage that are used in a read operation. | 06-13-2013 |
20130148890 | DIGITAL IMAGE PROCESSING APPARATUS AND METHOD - A digital image processing apparatus and method are provided. The digital image processing apparatus includes: a Y component processing unit receiving a Y component and performing edge enhancement processing and first noise reduction processing on the Y component by using a memory allocated to the Y component; and a CbCr processing unit receiving a Cb component and a Cr component, and performing false color suppression processing and second noise reduction processing on the Cb component and the Cr component by using a memory allocated to the Cb component and the Cr component, where the Y component, the Cb component and the Cr component are variables of the YCbCr color space. | 06-13-2013 |
20130151176 | SEMICONDUCTOR APPARATUS AND CHIP SELECTING METHOD THEREOF - A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating code of different values; an individual chip activation block configured to enable an individual chip activation signal among a plurality of individual chip activation signals, which corresponds to individual chip designating code, when the individual chip designating code matches the individual chip control code; and a control block configured to set the individual chip control code or output chip selection address as the individual chip control code in response to chip selection fuse signals and test fuse signals. | 06-13-2013 |
20130153990 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor device and a method for manufacturing the same, a pillar pattern is formed in an alternating pattern and a one side contact (OSC) is formed without using a tilted ion implantation process or a mask, resulting in formation of a vertical gate. The semiconductor device includes an alternating or zigzag-type pillar pattern formed over a semiconductor substrate, a first hole formed between pillars of the pillar pattern, a passivation layer formed over a sidewall of the first hole, a second hole formed by partially etching a lower part of the first hole, a bit line formed in the second hole, and a contact formed at a lower part of the pillar pattern. | 06-20-2013 |
20130155775 | METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is operated by reading data stored in LSB and MSB pages of a first word line in response to a read command and storing the read data in first and second latches of a page buffer, outputting the data stored in the first latch externally and transferring the data, stored in the second latch, to a third latch of the page buffer, resetting the first and second latches, reading data stored in LSB and MSB pages of a second word line, and storing the read data in the first and second latches, and sequentially outputting the data stored in the first latch and the data stored in the third latch, resetting the third latch, and then transferring the data stored in the second latch to the third latch. | 06-20-2013 |
20130166993 | ERROR DETECTING CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME - An error detecting circuit of a semiconductor apparatus, comprising: a fail detecting section configured to receive 2-bit first test data signals outputted from a first block and 2-bit second test data signals outputted from a second block, disable a first fail detection signal when the 2-bit first test data signals have different levels, disable a second fail detection signal when the 2-bit second test data signals have different levels, and disable both the first and second fail detection signals when the 2-bit first test data signals have the same level, the 2-bit second test data signals have the same level, and levels of the 2-bit first test data signals and the 2-bit second test data signals are the same with each other. | 06-27-2013 |
20130168814 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor device and a method for manufacturing the same, a mesh shaped lower electrode of a peripheral region is used as a reservoir capacitor to increase the size of a region contacting a dielectric film, such that Cs deterioration is minimized. An exemplary semiconductor device may include a line-type storage node contact plug formed over a semiconductor substrate, a mesh shaped lower electrode formed over the storage node contact plug, and a dielectric film and an upper electrode formed over the lower electrode. | 07-04-2013 |
20130168875 | SEMICONDUCTOR DEVICE AND PACKAGE - A semiconductor device includes a semiconductor substrate having an upper surface, a lower surface, a first side and a second side, wherein the lower surface has a slope so that the first side is thicker than the second side, and a circuit pattern including a bonding pad on the upper surface of the semiconductor substrate. | 07-04-2013 |
20130178064 | POLISHING SLURRY AND CHEMICAL MECHANICAL PLANARIZATION METHOD USING THE SAME - A polishing slurry for a chemical mechanical planarization process includes polishing particles and polyhedral nanoscale particles having a smaller size than the polishing particles and including a bond of silicon (Si) and oxygen (O). | 07-11-2013 |
20130189608 | EXTREME ULTRA VIOLET (EUV) MASK - An extreme ultra violate (EUV) mask is disclosed, which prevents defects from shot overlap encountered in wafer exposure as well as reflection of unnecessary EUV and DUV generated in a black border region, such that a pattern CD is reduced and defects are not created. The EUV mask includes a quartz substrate, a multi-layered reflection film formed over the quartz substrate to reflect exposure light, an absorption layer formed over the multi-layered reflection film, a black border region formed over the quartz substrate that does not include the multi-layered reflection film, and a blind layer formed in a position including at least one of over the absorption layer, over the quartz substrate, and below the quartz substrate. | 07-25-2013 |
20130196256 | REFLECTION-TYPE PHOTOMASKS AND METHODS OF FABRICATING THE SAME - Reflection-type photomasks are provided. The reflection-type photomask includes a substrate and a reflection layer on a front surface of the substrate. The substrate includes a pattern transfer region, a light blocking region and a border region. A trench penetrates the reflection layer in the border region to expose the substrate. First absorption layer patterns are disposed on the reflection layer in the pattern transfer region, and a second absorption layer pattern is disposed on the reflection layer in the light blocking region. Sidewalls of the trench have a sloped profile. Related methods are also provided. | 08-01-2013 |
20130200453 | SEMICONDUCTOR DEVICES INCLUDING BIPOLAR TRANSISTORS, CMOS TRANSISTORS AND DMOS TRANSISTORS, AND METHODS OF MANUFACTURING THE SAME - Semiconductor devices having a bipolar transistor, a CMOS transistor, a drain extension MOS transistor and a double diffused MOS transistor are provided. The semiconductor device includes a semiconductor substrate including a logic region in which a logic device is formed and a high voltage region in which a high power device is formed, trenches in the semiconductor substrate, isolation layers in respective ones of the trenches, and at least one field insulation layer disposed at a surface of the semiconductor substrate in the high voltage region. Related methods are also provided. | 08-08-2013 |