Patent application number | Description | Published |
20090289240 | NON-VOLATILE MULTI-BIT MEMORY WITH PROGRAMMABLE CAPACITANCE - Non-volatile multi-bit memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A first solid electrolyte cell is over the insulating layer and has a capacitance that is controllable between at least two states and is proximate the source region. A second solid electrolyte cell is over the insulating layer and has a capacitance or resistance that is controllable between at least two states and is proximate the drain region. An insulating element isolates the first solid electrolyte cell from the second solid electrolyte cell. A first anode is electrically coupled to the first solid electrolyte cell. The first solid electrolyte cell is between the anode and the insulating layer. A second anode is electrically coupled to the second solid electrolyte cell. The second solid electrolyte cell is between the anode and the insulating layer. A gate contact layer is over the substrate and between the source region and drain region and in electrical connection with the first anode and the second anode. The gate contact layer is electrically coupled to a voltage source. | 11-26-2009 |
20090289290 | NON-VOLATILE MEMORY WITH PROGRAMMABLE CAPACITANCE - Non-volatile memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A second insulating layer is over the substrate and between the source region and drain region. A solid electrolyte layer is between the first insulating layer and second insulating layer. The solid electrolyte layer has a capacitance that is controllable between at least two states. A first electrode is electrically coupled to a first side of the solid electrolyte layer and is electrically coupled to a voltage source. A second electrode is electrically coupled to a second side of the solid electrolyte layer and is electrically coupled to the voltage source. Multi-bit memory units are also disclosed. | 11-26-2009 |
20100006813 | PROGRAMMABLE METALLIZATION MEMORY CELLS VIA SELECTIVE CHANNEL FORMING - A programmable metallization memory cell that has an apertured insulating layer comprising at least one aperture therethrough positioned between the active electrode and the inert electrode. Superionic clusters are present within the at least one aperture, and may extend past the at least one aperture. Also, methods for making a programmable metallization memory cell are disclosed. | 01-14-2010 |
20100038735 | MAGNET-ASSISTED TRANSISTOR DEVICES - A transistor device includes a magnetic field source adapted to deflect a flow of free electron carriers within a channel of the device, between a source region and a drain region thereof. According to preferred configurations, the magnetic field source includes a magnetic material layer extending over a side of the channel that is opposite a gate electrode of the transistor device. | 02-18-2010 |
20100072448 | PLANAR PROGRAMMABLE METALLIZATION MEMORY CELLS - Programmable metallization memory cells that have an inert electrode and an active electrode positioned in a non-overlapping manner in relation to a substrate. A fast ion conductor material is in electrical contact with and extends from the inert electrode to the active electrode, the fast ion conductor including superionic clusters extending from the inert electrode to the active electrode. A metal layer extends from the inert electrode to the active electrode, yet is electrically insulated from each of the inert electrode and the active electrode by the fast ion conductor material. Methods for forming programmable metallization cells are also disclosed. | 03-25-2010 |
20100084724 | MEMORY CELL WITH STRESS-INDUCED ANISOTROPY - A magnetic memory element that has a stress-induced magnetic anisotropy. The memory element has a ferromagnetic free layer having a switchable magnetization orientation switchable, a ferromagnetic reference layer having a pinned magnetization orientation, and a non-magnetic spacer layer therebetween. The free layer may be circular, essentially circular or nearly circular. | 04-08-2010 |
20100109107 | MAGNETIC STACK DESIGN WITH DECREASED SUBSTRATE STRESS - A magnetic element and a method for making a magnetic element. The method includes patterning a first electrode material to form a first electrode on a substrate and depositing filler material on the substrate around the first electrode. The method further includes polishing to form a planar surface of filler and the first electrode. A magnetic cell is formed on the planar surface and a second electrode is formed on the magnetic cell. In some embodiments, the first electrode has an area that is at least 2:1 to the area of the magnetic cell. | 05-06-2010 |
20100197104 | PROGRAMMABLE METALLIZATION MEMORY CELLS VIA SELECTIVE CHANNEL FORMING - Methods for making a programmable metallization memory cell are disclosed. | 08-05-2010 |
20100309717 | NON-VOLATILE MULTI-BIT MEMORY WITH PROGRAMMABLE CAPACITANCE - Non-volatile multi-bit memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region; and a gate stack structure over the substrate and between the source region and drain region. The gate stack structure includes a first solid electrolyte cell and a second solid electrolyte cell. The solid electrolyte cells having a capacitance that is controllable between at least two states. A gate contact layer is electrically coupled to a voltage source. The first solid electrolyte cell and the second solid electrolyte cell separate the gate contact layer from the substrate. | 12-09-2010 |
20100327248 | CELL PATTERNING WITH MULTIPLE HARD MASKS - A method of making a memory cell or magnetic element by using two hard masks. The method includes first patterning a second hard mask to form a reduced second hard mask, with a first hard mask being an etch stop for the patterning process, and then patterning the first hard mask to form a reduced first hard mask by using the reduced second hard mask as a mask and using an etch stop layer as an etch stop. After patterning both hard masks, then patterning a functional layer by using the reduced first hard mask as a mask. In the resulting memory cell, the first hard mask layer is also a top lead, and the diameter of the first hard mask layer is at least essentially the same as the diameter of the etch stop layer, the adhesion layer, and the functional layer. | 12-30-2010 |
20110006436 | Conductive Via Plug Formation - Various embodiments of the present invention are generally directed to a method of forming a conductive via plug in a semiconductor device. A first and second metal layer are electrically connected by a via plug that is formed by depositing a tungsten seed layer on a plurality of metal barrier layers within a recess using atomic layer deposition. The recess is then filled with tungsten using chemical vapor deposition. | 01-13-2011 |
20110007552 | Active Protection Device for Resistive Random Access Memory (RRAM) Formation - Apparatus and method for providing overcurrent protection to a resistive random access memory (RRAM) cell during an RRAM formation process used to prepare the cell for normal read and write operations. In accordance with various embodiments, the RRAM cell is connected between a first control line and a second control line, and an active protection device (APD) is connected between the second control line and an electrical ground terminal. A formation current is applied through the RRAM cell, and an activation voltage is concurrently applied to the APD to maintain a maximum magnitude of the formation current below a predetermined threshold level | 01-13-2011 |
20110193148 | MAGNET-ASSISTED TRANSISTOR DEVICES - A transistor device includes a magnetic field source adapted to deflect a flow of free electron carriers within a channel of the device, between a source region and a drain region thereof. According to preferred configurations, the magnetic field source includes a magnetic material layer extending over a side of the channel that is opposite a gate electrode of the transistor device. | 08-11-2011 |
20110267873 | NON-VOLATILE MEMORY WITH PROGRAMMABLE CAPACITANCE - Non-volatile memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A second insulating layer is over the substrate and between the source region and drain region. A solid electrolyte layer is between the first insulating layer and second insulating layer. The solid electrolyte layer has a capacitance that is controllable between at least two states. A first electrode is electrically coupled to a first side of the solid electrolyte layer and is electrically coupled to a voltage source. A second electrode is electrically coupled to a second side of the solid electrolyte layer and is electrically coupled to the voltage source. Multi-bit memory units are also disclosed. | 11-03-2011 |
20120104348 | PROGRAMMABLE METALLIZATION MEMORY CELLS VIA SELECTIVE CHANNEL FORMING - Methods for making a programmable metallization memory cell are disclosed. | 05-03-2012 |
20130187115 | PROGRAMMABLE METALLIZATION MEMORY CELLS VIA SELECTIVE CHANNEL FORMING - Programmable metallization memory cells include an electrochemically active electrode, an inert electrode and an internal layer between the electrochemically active electrode and the inert electrode. The internal layer having a fast ion conductor material and an apertured layer having a plurality of apertures defined by an electrically insulating material. Each aperture defines at least a portion of a column of fast ion conductor material having superionic clusters. | 07-25-2013 |