Shrinivas
Shrinivas Ashwin, Sammamish, WA US
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20090077253 | ENHANCED TABULAR DATA STREAM PROTOCOL - Systems and methodologies are provided as part of a computing environment that implements an enhanced tabular data stream (TDS) protocol. Such enhanced TDS protocol can mitigate synchronization inconsistencies between client and servers, improve robustness of the data transfer, facilitate password specification as part of login procedures, and reduce administration overhead. Various headers are provided as part of the data stream protocol, and a versioning scheme is established that facilitates proper communication between servers and clients having different release dates and versions of the TDS protocol. | 03-19-2009 |
Shrinivas Bairi, San Diego, CA US
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20090193519 | Systems and Methods for Accessing a Tamperproof Storage Device in a Wireless Communication Device Using Biometric Data - A novel system and method for accessing data stored in a secure or tamperproof storage device in a wireless communication device is provided. The wireless communication device may include a biometric sensor for capturing a biometric sample of the user. The captured biometric sample may be compared to known biometric samples of users stored in a memory device of the wireless communication device. If the captured biometric sample matches one of the known biometric samples, the user is allowed access to the tamperproof storage device for a preset amount of time. The user may delete existing data, add new data, modify existing data or view existing data stored in the tamperproof storage device. | 07-30-2009 |
Shrinivas Nagaraddi, Bengaluru IN
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20150310159 | COMPUTER-IMPLEMENTED VERIFICATION SYSTEM FOR PERFORMING A FUNCTIONAL VERIFICATION OF AN INTEGRATED CIRCUIT - A computer-implemented verification system for performing a system level or a system on chip level functional verification of integrated circuit is provided. The computer-implemented system includes one or more processors and a memory storing instructions defined by one or more modules of including a scenario compiler, a verification component and a software library component. The scenario compiler receives a set of verification scenario intents including at least one of test-application intents, constraints, device-programming intents and scenario-control intents. The scenario compiler generates one or more open verification methodology (OVM) and/or universal verification methodology (UVM) compliant test bench sequences and one or more scenario software implementations based on the set of verification scenario intents. The verification component interacts with the integrated circuit using the OVM and/or UVM compliant test bench sequences. The software library component enables execution of the scenario software implementations on a processing unit core of the integrated circuit. | 10-29-2015 |
Shrinivas Pundlik, Boston, MA US
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20150243044 | Collision Prediction - In some implementations, there is provided a method. The method may include receiving data characterizing a plurality of digital video frames; detecting a plurality of features in each of the plurality of digital video frames; determining, from the detected features, a local scale change and a translational motion of one or more groups of features between at least a pair of the plurality of digital video frames; and calculating a likelihood of collision. Related apparatus, systems, techniques, and articles are also described. | 08-27-2015 |
Shrinivas Sureban, Bangalore IN
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20100268854 | SYSTEM AND METHOD FOR UTILIZING PERIPHERAL FIRST-IN-FIRST-OUT (FIFO) RESOURCES - A system and method for sharing peripheral first-in-first-out (FIFO) resources is disclosed. In one embodiment, a system for utilizing peripheral FIFO resources includes a processor, a first peripheral FIFO controller and a second peripheral FIFO controller coupled to the processor for controlling buffering of first data and second data associated with the processor respectively. Further, the system includes a merge module coupled to the first peripheral FIFO controller and the second peripheral FIFO controller for merging a first FIFO channel associated with the first peripheral FIFO controller and a second FIFO channel associated with the second peripheral FIFO controller based on an operational state of the first FIFO channel and an operational state of the second FIFO channel respectively. Also, the system includes a first FIFO and a second FIFO coupled to the merge module via the first FIFO channel and the second FIFO channel respectively. | 10-21-2010 |
20120311210 | SYSTEM AND METHOD FOR OPTIMIZING SLAVE TRANSACTION ID WIDTH BASED ON SPARSE CONNECTION IN MULTILAYER MULTILEVEL INTERCONNECT SYSTEM-ON-CHIP ARCHITECTURE - A system and method for optimizing slave transaction ID width based on sparse connection between multiple masters and multiple slaves in a multilayer multilevel interconnect system-on-chip (SOC) architecture are disclosed. In one embodiment, slave transaction ID widths are computed for a first processing subsystem and a second processing subsystem including multiple masters and multiple slaves. Further, a slave transaction ID for each master to any slave in the first processing subsystem and in the second processing subsystem is generated based on the computed slave transaction ID width. Furthermore, sparse connection information between the multiple masters and multiple slaves is determined via a first bus matrix in the first processing subsystem. A first optimized slave transaction ID for each master to any slave in the first processing subsystem is then generated by removing don't care bits in each generated slave transaction ID based on the sparse connection information. | 12-06-2012 |
20140006644 | Address Remapping Using Interconnect Routing Identification Bits | 01-02-2014 |