Shishlov
Sergey Shishlov, Moscow RU
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20130339679 | METHOD AND APPARATUS FOR REDUCING AREA AND COMPLEXITY OF INSTRUCTION WAKEUP LOGIC IN A MULTI-STRAND OUT-OF-ORDER PROCESSOR - A computer system, a computer processor and a method executable on a computer processor involve placing each sequence of a plurality of sequences of computer instructions being scheduled for execution in the processor into a separate queue. The head instruction from each queue is stored into a first storage unit prior to determining whether the head instruction is ready for scheduling. For each instruction in the first storage unit that is determined to be ready, the instruction is moved from the first storage unit to a second storage unit. During a first processor cycle, each instruction in the first storage unit that is determined to be not ready is retained in the first storage unit, and the determining of whether the instruction is ready is repeated during the next processor cycle. Scheduling logic performs scheduling of instructions contained in the second storage unit. | 12-19-2013 |
20130339711 | METHOD AND APPARATUS FOR RECONSTRUCTING REAL PROGRAM ORDER OF INSTRUCTIONS IN MULTI-STRAND OUT-OF-ORDER PROCESSOR - A computer system, a processor in a computer and a computer-implemented method executable on a computer processor involve dividing a set of computer instructions arranged in a sequential program order into a plurality of instruction sequences. Instructions within each sequence are arranged according to the program order. An increment value is assigned to a preceding instruction in each sequence. The increment value is equal to a difference between a program order value of a subsequent instruction in the sequence and a program order value of the preceding instruction. The processor calculates the program order value of each subsequent instruction based on the program order value and the increment value of a corresponding preceding instruction in the same sequence. | 12-19-2013 |
Sergey B. Shishlov, Melbourne, IA US
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20160131739 | DISPLAY SYSTEM AND METHOD USING WEATHER RADAR SENSING - An enhanced vision method uses or an enhanced vision system includes an onboard weather radar system configured to improve angular resolution and/or resolution in range. The onboard weather radar system generates image data representative of the external scene topography of a runway environment associated with radar returns received by the onboard weather radar system. The radar returns are in an X-band or a C-band. The enhanced vision system also includes a display in communication with the onboard weather radar system and is configured to display an image associated with the image data that is generated by the onboard weather radar system. The enhanced vision system can also be used as an enhanced flight vision system. | 05-12-2016 |
Sergey Y. Shishlov, Moscow RU
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20130007415 | METHOD AND APPARATUS FOR SCHEDULING OF INSTRUCTIONS IN A MULTI-STRAND OUT-OF-ORDER PROCESSOR - In accordance with embodiments disclosed herein, there are provided methods, systems, and apparatuses for scheduling instructions in a multi-strand out-of-order processor. For example, an apparatus for scheduling instructions in a multi-strand out-of-order processor includes an out-of-order instruction fetch unit to retrieve a plurality of interdependent instructions for execution from a multi-strand representation of a sequential program listing; an instruction scheduling unit to schedule the execution of the plurality of interdependent instructions based at least in part on operand synchronization bits encoded within each of the plurality of interdependent instructions; and a plurality of execution units to execute at least a subset of the plurality of interdependent instructions in parallel. | 01-03-2013 |
20140208074 | INSTRUCTION SCHEDULING FOR A MULTI-STRAND OUT-OF-ORDER PROCESSOR - In one embodiment, a multi-strand system with a pipeline includes a front-end unit, an instruction scheduling unit (ISU), and a back-end unit. The front-end unit performs an out-of-order fetch of interdependent instructions queued using a front-end buffer. The ISU dedicates two hardware entries per strand for checking operand-readiness of an instruction and for determining an execution port to which the instruction is dispatched. The back-end unit receives instructions dispatched from the hardware device and stores the instructions until they are executed. Other embodiments are described and claimed. | 07-24-2014 |
20150301831 | SELECT LOGIC FOR THE INSTRUCTION SCHEDULER OF A MULTI STRAND OUT-OF-ORDER PROCESSOR BASED ON DELAYED RECONSTRUCTED PROGRAM ORDER - A processing device comprises select logic to schedule a plurality of instructions for execution. The select logic calculates a reconstructed program order (RPO) value for each of a plurality of instructions that are ready to be scheduled for execution. The select logic creates an ordered list of instructions based on the delayed RPO values, the delayed RPO values comprising the calculated RPO values from a previous execution cycle, and dispatches instructions for scheduling based on the ordered list. | 10-22-2015 |
20160092367 | HARDWARE APPARATUSES AND METHODS TO CONTROL ACCESS TO A MULTIPLE BANK DATA CACHE - Methods and apparatuses to control access to a multiple bank data cache are described. In one embodiment, a processor includes conflict resolution logic to detect multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle and to grant access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache. In another embodiment, a method includes detecting multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle, and granting access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache. | 03-31-2016 |
Sergey Yu. Shishlov, Moscow RU
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20100274972 | SYSTEMS, METHODS, AND APPARATUSES FOR PARALLEL COMPUTING - Systems, methods, and apparatuses for parallel computing are described. In some embodiments, a processor is described that includes a front end and back end. The front includes an instruction cache to store instructions of a strand. The back end includes a scheduler, register file, and execution resources to execution the strand's instructions. | 10-28-2010 |