Patent application number | Description | Published |
20100165691 | CONTENT ADDRESSABLE MEMORY - An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. | 07-01-2010 |
20120170344 | CONTENT ADDRESSABLE MEMORY - An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased. | 07-05-2012 |
20130010513 | CONTENT ADDRESSABLE MEMORY - An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased. | 01-10-2013 |
20130082737 | SEMICONDUCTOR DEVICE HAVING SERIALIZER CONVERTING PARALLEL DATA INTO SERIAL DATA TO OUTPUT SERIAL DATA FROM OUTPUT BUFFER CIRCUIT - Disclosed herein is a device that includes first and second buffer circuits connected to a data terminal and a first control circuit controlling the first and second buffer circuits. The first control circuit receives n pairs of first and second internal data signals complementary to each other from 2 n input signal lines and outputs a pair of third and fourth internal data signals complementary to each other to first and second output signal lines, where n is a natural number more than one. The first and second buffer circuits are controlled based on the third and fourth internal data signals such that one of the first and second buffer circuits turns on and the other of the first and second buffer circuits turns off. | 04-04-2013 |
20130082743 | SEMICONDUCTOR DEVICE GENERATES COMPLEMENTARY OUTPUT SIGNALS - A splitter circuit in a semiconductor device includes a first inverter that receives an input signal and outputs an inverted signal, a second inverter that receives the inverted signal and outputs a non-inverted signal (a first output signal), a third inverter that receives the input signal and outputs an inverted signal (a second output signal) and an auxiliary inverter that shares an output signal line with the third inverter. The third inverter and the auxiliary inverter use an inverted signal of the input signal as power supplies. | 04-04-2013 |
20130082758 | SEMICONDUCTOR DEVICE HAVING OUTPUT BUFFER CIRCUIT IN WHICH IMPEDANCE THEREOF CAN BE CONTROLLED - Disclosed herein is a device that includes a first buffer circuit coupled between a first power supply line and a data terminal and a second buffer circuit coupled between a second power supply line and the data terminal. First and second internal data signals complementary to each other are supplied to a level shifter, thereby third and fourth internal data signals complementary to each other are generated by changing amplitude values of the first and second internal data signals. The first and the second buffer circuits are controlled based on the third and fourth internal data signals such that one of the first and second buffer circuits turns on and the other of the first and second buffer circuits turns off. | 04-04-2013 |
20130091327 | SEMICONDUCTOR DEVICE PERFORMING BURST ORDER CONTROL AND DATA BUS INVERSION - Disclosed herein is a device that a device including first data lines transmitting a plurality of sequential first data bits, respectively, second data lines transmitting a plurality of sequential second data bits, respectively, third data lines transmitting a plurality of sequential third data bits, respectively, a BOC circuit rearranging order of the plurality of first data bits supplied from the plurality of first data lines in accordance with address information, the BOC circuit supplying the resultant to the plurality of second data lines as the plurality of second data bits, and a DBI circuit performing inversion or non-inversion of the plurality of second data bits supplied from the plurality of second data lines independently of each other in accordance with a predetermined condition, the DBI circuit supplying the resultant to the plurality of third data lines as the plurality of third data bits. | 04-11-2013 |
20140126264 | CONTENT ADDRESSABLE MEMORY - An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased. | 05-08-2014 |
20150058011 | INFORMATION PROCESSING APPARATUS, INFORMATION UPDATING METHOD AND COMPUTER-READABLE STORAGE MEDIUM - An information processing apparatus recognizes input data as character information formed by character strings each being in a predetermined unit based on information relating to a character string as a recognition target, and performs processing based on the recognized character information. The apparatus includes an input information receiver that receives input information capable of being processed as characters; an input information dividing unit that divides the received input information into character strings each being in a predetermined processing unit; a popularity level calculating unit that calculates a popularity level based on history of an appearance timing of each of the divided character strings, the popularity level indicating information relating to a usage frequency for a predetermined period of time up to a current time for each of the divided character strings; and an updating processor that updates the information relating to the character string based on the calculated popularity level. | 02-26-2015 |