Patent application number | Description | Published |
20140019512 | PARALLEL COMPUTING SYSTEM AND CONTROL METHOD OF PARALLEL COMPUTING SYSTEM - A parallel computing system includes: each computing node including: a first channel receiving data which a preceding node transfers, and transferring received data to a subsequent node; a second channel receiving data which a preceding node transfers, and transferring received data to a subsequent node; and a computational processor receiving data which the first or second channel has received, and transferring processed data to a subsequent node; an input-output node including: a third channel receiving data which the first channel or the computational processor of a preceding node transfers; a fourth channel receiving data which the first channel or the computational processor of a preceding computing node transfers, and transferring the received data to the second channel of a subsequent computing node; and an input-output processor receiving data which the third channel has received, and transferring inputted and outputted data to the first channel of a subsequent computing node. | 01-16-2014 |
20140023090 | PARALLEL COMPUTING DEVICE, COMMUNICATION CONTROL DEVICE, AND COMMUNICATION CONTROL METHOD - A parallel computing device includes a plurality of communicatively interconnected nodes for executing an arithmetic process. Each of the plurality of nodes includes: a measurement unit configured to measure a communication bandwidth up to a destination node based on a communication scheme among the nodes, and a control unit configured to control a size of a packet transmitted to the destination node according to the communication bandwidth measured by the measurement unit. | 01-23-2014 |
20140040558 | INFORMATION PROCESSING APPARATUS, PARALLEL COMPUTER SYSTEM, AND CONTROL METHOD FOR ARITHMETIC PROCESSING UNIT - An information processing apparatus included in a parallel computer system has a memory that holds data and a processor including a cache memory that holds a part of the data held on the memory and a processor core that performs arithmetic operations using the data held on the memory or the cache memory. Moreover, the information processing apparatus has a communication device that determines whether data received from a different information processing apparatus is data that the processor core waits for. When the communication device determines that the received data is data that the processor core waits for, the communication device stores the received data on the cache memory. When the communication device determines that the received data is data that the processor core does not wait for, the communication device stores the received data on the memory. | 02-06-2014 |
20140047157 | PARALLEL COMPUTER SYSTEM, CROSSBAR SWITCH, AND METHOD OF CONTROLLING PARALLEL COMPUTER SYSTEM - A parallel computer system includes a plurality of processors including a first processor and a plurality of second processors; and a crossbar switch provided with a plurality of ports; wherein the first processor transmits data to a first port among the plurality of ports, and transmits standby time information to the first port in the case where the plurality of second processors are unable to transmit data to the first port despite receiving a communication authorization notification from the first port, and the first port receives the standby time information, and after the standby time elapses, selects one of the plurality of second processors. | 02-13-2014 |
20140052885 | PARALLEL COMPUTER SYSTEM, DATA TRANSFER DEVICE, AND METHOD FOR CONTROLLING PARALLEL COMPUTER SYSTEM - A switch includes a plurality of ports and a combination determining unit that determines a central processing unit (CPU) to be paired with one of the ports. The port includes: an arbitration circuit that selects the CPU to be paired therewith when receiving an arbitration request from the CPU to be paired in a predetermined state, and selects one of the CPUs from which the arbitration request has been received in other cases to return transmission permission; and a data transfer unit that transfers the received data from the selected CPU to another CPU. The CPU includes: a request transmission unit that transmits the arbitration request to the ports; and a data transmission unit that transmits data to the paired port when the arbitration request is transmitted to the paired port in the predetermined state, and transmits data to the ports that have returned transmission permission in other cases. | 02-20-2014 |
20140198658 | DATA COMMUNICATION APPARATUS, DATA TRANSMISSION METHOD, AND COMPUTER SYSTEM - Provided is a data communication apparatus which includes a transmission interval calculator configured to calculate an effective transfer speed of the data based on a difference between an actual arrival time at which response data to transmission data transmitted to the other data communication apparatus has arrived and a predictive arrival time calculated by multiplying the number of relay devices passed until the response data from the other data communication apparatus arrives at the data communication apparatus by a transfer delay time necessary to pass through one relay device and a buffer size of the relay device on a communication path of the data, and calculate a transmission interval of transmission data based on the effective transfer speed and a transmission controller configured to perform transmission control of transmission data based on the transmission interval. Thus, congestion control is efficiently implemented in an interconnection network configured as a regular network. | 07-17-2014 |
20140293797 | COMPUTER SYSTEM, COMMUNICATIONS CONTROL DEVICE, AND CONTROL METHOD FOR COMPUTER SYSTEM - In a case where data is output, a transmission node number stored by a transmission node number storing unit is updated. As a result of comparison between a transmission node number included in data input by an input unit and the transmission node number stored by the transmission node number storing unit, in a case where the transmission node number stored by the transmission node number storing unit is larger than the transmission node number included in the data input by the input unit, by overwriting the transmission node number included in data output by an output unit with the transmission node number stored in the transmission node number storing unit, congestion control matching the communication state of a communication route can be efficiently realized. | 10-02-2014 |
20150154115 | PARALLEL COMPUTER SYSTEM, CONTROL METHOD OF PARALLEL COMPUTER SYSTEM, INFORMATION PROCESSING DEVICE, ARITHMETIC PROCESSING DEVICE, AND COMMUNICATION CONTROL DEVICE - A parallel computer system includes information processing devices, each of the information processing devices including a communication control device that performs communication, a main memory that stores data, and an arithmetic processing device that is coupled to the communication control device and the main memory, the information processing devices being coupled to each other through a network by the respective communication control device, wherein the arithmetic processing device includes a cache memory and a cache controller, the cache controller that executes an atomic operation for target data on the cache memory that stores the target data when the communication control device outputs an atomic operation request that is used to request the atomic operation, the atomic operation being not divided into a smaller operation, and notifies the communication control device of a result that is obtained by executing the atomic operation on the cache memory. | 06-04-2015 |