Patent application number | Description | Published |
20130031039 | APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING SPIKE EVENT IN NEUROMORPHIC CHIP - An apparatus and a method for transmitting and receiving a spike event in a neuromorphic chip. A transmission apparatus of the neuromorphic chip outputs addresses sequentially and repeatedly to an address bus, and when a spike generated by a neuron is detected by the transmission apparatus, outputs a strobe at a first time when one of the addresses being output sequentially and repeatedly becomes identical to an address of the neuron that generated the spike. A receiving apparatus of the neuromorphic chip inputs an address through the address bus at a strobe detection time when the strobe is detected by the receiving apparatus. | 01-31-2013 |
20130151451 | NEURAL WORKING MEMORY DEVICE - A spiking neuron-based working memory device is provided. The spiking neuron-based working memory device includes an input interface configured to convert input spike signals into respective burst signals having predetermined forms, and output a sequence of the burst signals, the burst signals corresponding to the input spike signals in a burst structure, and two or more memory elements (MEs) configured to sequentially store features respectively corresponding to the outputted sequence of the burst signals, each of the MEs continuously outputting spike signals respectively corresponding to the stored features. | 06-13-2013 |
20130329524 | NEUROMORPHIC SIGNAL PROCESSING DEVICE ANDMETHOD FOR LOCATING SOUND SOURCE USING A PLURALITYOF NEURON CIRCUITS - Provided is a neuromorphic signal processing device for locating a sound source using a plurality of neuron circuits, the neuromorphic signal processing device including a detector configured to output a detected spiking signal using a detection neuron circuit corresponding to a predetermined time difference, in response to a first signal and a second signal containing an identical input spiking signal with respect to the predetermined time difference, for each of a plurality of predetermined frequency bands, a multiplexor configured to output a multiplexed spiking signal corresponding to the predetermined time difference based on a plurality of the detected spiking signals output from a plurality of neuron circuits corresponding to the plurality of frequency bands, and an integrator configured to output an integrated spiking signal corresponding to the predetermined time difference, based on a plurality of the multiplexed spiking signals corresponding to a plurality of predetermined time differences. | 12-12-2013 |
20130335595 | EVENT-BASED IMAGE PROCESSING APPARATUS AND METHOD - Provided is an event-based image processing apparatus and method, the apparatus including a sensor which senses occurrences of a predetermined event in a plurality of image pixels and which outputs an event signal in response to the sensed occurrences, a time stamp unit which generates time stamp information by mapping a pixel corresponding to the event signals to a time at which the event signals are output from the sensor, and an optical flow generator which generates an optical flow based on the time stamp information in response to the outputting of the event signals. | 12-19-2013 |
20140320706 | METHOD AND APPARATUS FOR SENSING SPATIAL INFORMATION BASED ON VISION SENSOR - Apparatuses and methods for sensing spatial information based on a vision sensor are disclosed. The apparatus and method recognize the spatial information of an object sensed by the vision sensor that senses a temporal change of light. The light being input into the vision sensor is artificially changed using a change unit configured to change the light being input to the vision sensor. | 10-30-2014 |
20140351753 | METHOD AND APPARATUS FOR USER INTERFACE BASED ON GESTURE - A method for a user interface based on a gesture includes setting at least one gesture region including at least one basic region and at least one navigation region based on a preset location or a detected location of at least one object to be tracked, the at least one navigation region including at least one item, detecting a gesture of the at least one object to be tracked using an input device, and recognizing, from the detected gesture, at least one of a select gesture for selecting any one item among the at least one item of the at least one navigation region and a confirm gesture for moving from the at least one navigation region to the at least one basic region. | 11-27-2014 |
20140354537 | APPARATUS AND METHOD FOR PROCESSING USER INPUT USING MOTION OF OBJECT - A user input processing apparatus using a motion of an object to determine whether to track the motion of the object, and track the motion of the object using an input image including information associated with the motion of the object. | 12-04-2014 |
Patent application number | Description | Published |
20100091593 | SEMICONDUCTOR MEMORY DEVICE INCLUDING SIGNAL CONTROLLER CONNECTED BETWEEN MEMORY BLOCKS - A semiconductor memory device includes a first memory block, a second memory block, and a signal controller. The first memory block is configured to generate a first blocking signal, a second blocking signal, and a first enable signal in response to a row address, and to block and enable wordlines of the memory block in response to the first blocking signal and the first enable signal, respectively. The second memory block is configured to generate a third blocking signal, a fourth blocking signal, and a second enable signal in response to the row address, and to block and enable wordlines of the second memory block in response to the third blocking signal and the second enable signal, respectively. The signal controller is connected between the first memory block and the second memory block and is configured to enable the third blocking signal when the second blocking signal is enabled, and to enable the first blocking signal when the fourth blocking signal is enabled. | 04-15-2010 |
20100128514 | Semiconductor memory devices having bit lines - A semiconductor device includes a bit line connected to a plurality of memory cells in a memory block and a sense amplifier having a first node connected to the bit line and a second node, which is not connected to any bit line. The second node has a capacitive load less than that of the bit line. The sense amplifier amplifies a first data using a voltage difference between the first node and the second node caused by a charge sharing operation, and a second data using a capacitive mismatch between the first node and the second node. | 05-27-2010 |
20110044121 | SEMICONDUCTOR MEMORY DEVICE HAVING DEVICE FOR CONTROLLING BIT LINE LOADING AND IMPROVING SENSING EFFICIENCY OF BIT LINE SENSE AMPLIFIER - A semiconductor memory device includes a memory cell array block including a plurality of memory cells each connected to one of a plurality of bit lines and one of a plurality of word lines, a sense amplifier connected to a half of the plurality of bit lines, the sense amplifier for sensing and amplifying a voltage between each of the half of the bit lines and a corresponding complementary bit line; and a dummy block connected to the half of the plurality of bit lines of the memory cell array block, the dummy block for controlling a load on the memory cell array block to be different from a load on the dummy block according to a dummy load signal. | 02-24-2011 |
20140233336 | SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - A semiconductor device may comprise a first bit line, a second bit line, a memory cell connected to the first bit line, a bit line sense amplifier circuit and a control circuit. The bit line sense amplifier circuit may be coupled to the memory cell. The bit line sense amplifier circuit may include a first inverter having an input node coupled to the first bit line and an output node coupled to the second bit line, and a second inverter having an input node coupled to the second bit line and an output node coupled to the first bit line. The control circuit may be configured to activate the first inverter without activating the second inverter during a first time period and to activate the first inverter and the second inverter at the same time during a second time period after the first time period. | 08-21-2014 |
Patent application number | Description | Published |
20100230811 | SEMICONDUCTOR DEVICE HAVING A CONDUCTIVE BUMP - In one embodiment, a semiconductor device includes a semiconductor substrate and a bonding pad disposed thereon. The semiconductor device also includes a passivation layer, a buffer layer, and an insulating layer sequentially stacked on the semiconductor substrate. According to one aspect, a first recess is defined within the passivation layer, the buffer layer, and the insulating layer to expose at least a region of the bonding pad and a second recess is defined within the insulating layer to expose at least a region of the buffer layer and spaced apart from the first recess such that a portion of the insulating layer is interposed therebetween. Further, the semiconductor device includes a conductive solder bump disposed within the first and second recesses. The conductive solder bump may be connected to the bonding pad in the first recess and supported by the buffer layer through a protrusion of the conductive solder bump extending into the second recess. | 09-16-2010 |
20100259912 | Electronic device - Provided is an electronic device which may include a first structure having a first surface, a first land region on the first surface, a second structure having a second surface facing the first surface, a second land region on the second surface, and a connection structure between the first and second structures electrically connecting the first land region to the second land region. As provided, the first land region may have a major axis and a minor axis on the first surface and the second land region may have a major axis and a minor axis on the second surface. Furthermore, the major axes of the first and second land regions may have different orientations with respect to one another. | 10-14-2010 |
20110079897 | INTEGRATED CIRCUIT CHIP AND FLIP CHIP PACKAGE HAVING THE INTEGRATED CIRCUIT CHIP - In an integrated circuit (IC) chip and a flip chip package having the same, no wiring line is provided and the first electrode pad does not make contact with the wiring line in a pad area of the IC chip. Thus, the first bump structure makes contact with the first electrode regardless of the wiring line in the pad area. The second electrode pad makes contact with the wiring line in a pseudo pad area of the IC chip. Thus, the second bump structure in the pseudo pad area makes contact with an upper surface of the second electrode at a contact point(s) spaced apart from the wiring line under the second electrode. | 04-07-2011 |
Patent application number | Description | Published |
20100197186 | PHOTOALIGNMENT MATERIAL AND METHOD OF MANUFACTURING DISPLAY SUBSTRATE USING THE SAME - A photoalignment material and a method of manufacturing of a display substrate using the photoalignment material are disclosed. The photoalignment material includes a photoalignment polymer, a photoalignment additive, and an organic solvent. When the photoalignment additive is used, a side reaction due to ultraviolet (UV) light may be prevented, and the stability of alignment layer may be improved. | 08-05-2010 |
20110032464 | LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD FOR THE SAME - A liquid crystal display according to an exemplary embodiment of the present invention includes a first substrate and a second substrate facing each other and a liquid crystal layer formed between the first substrate and the second substrate and including liquid crystal molecules. The liquid crystal layer includes a first sub-region and a second sub-region having different alignment azimuth angles of the liquid crystal molecules, the liquid crystal molecules of the first sub-region are aligned to have a first azimuth angle and a polar angle of less than 90° near the first substrate and are vertically aligned near the second substrate, and the liquid crystal molecules of the second sub-region are aligned to have a second azimuth angle and a polar angle of less than 90° near the second substrate and are vertically aligned near the first substrate. | 02-10-2011 |
20110261307 | LIQUID CRYSTAL DISPLAY - In a liquid crystal display, a first alignment layer formed on a first substrate includes a first region aligned in a first direction and a second region aligned in a second direction opposite to the first direction, and a second alignment layer formed on a second substrate facing the first substrate includes a third region aligned in a third direction different from the first direction and a fourth region aligned in a fourth direction opposite to the third direction. The liquid crystal molecules interposed between the first and second alignment layers are aligned in different directions in different domains defined by the first to fourth regions. A pixel electrode includes an extension part extending in at least one of the first to fourth directions. The aperture ratio and the light transmittance of the liquid crystal display are improved. | 10-27-2011 |
20120196054 | LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD THEREOF - A liquid crystal display including: a first substrate and a second substrate facing each other; an alignment layer disposed on one of the first substrate and the second substrate and including a vertical photo-alignment material which includes a first vertical functional group and a photo-reactive group, and a major alignment material which does not include the photo-reactive group; and a liquid crystal layer disposed between the first substrate and the second substrate, wherein a ratio of a molar concentration of the vertical photo-alignment material to the molar concentration of the major alignment material increases in a direction towards a surface of the alignment layer adjacent to the liquid crystal layer. | 08-02-2012 |
20130251981 | INFRARED RAY BLOCKING MULTI-LAYERED STRUCTURE INSULATING FILM HAVING THERMAL ANISOTROPY - The present invention relates to an infrared blocking multi-layered insulating film having thermal anisotropy, the film comprising an infrared absorption layer comprising at least one of perovskite oxide dispersed sol, metallic oxide dispersed sol, and ITO or ATO; a thermal resistance layer located on or above one surface of the infrared absorption layer; and an emission layer located on or above another surface of the infrared absorption layer. An infrared blocking multi-layered insulating film having thermal anisotropy according to the present invention may control heat flow, thereby generating excellent insulating effect. | 09-26-2013 |
Patent application number | Description | Published |
20090236868 | Rear Bumper Assembly and Tail Trim Cover for Vehicle - A rear bumper assembly and a tail trim cover are disclosed herein. The rear bumper cover comprises a rear bumper cover having an exhaust hole portion, a main tail trim mounted to the exhaust hole portion, and a tail trim cover coupled to the main tail trim. Bent portions defining a gradually decreasing diameter are formed in a joint region between the main tail trim and the tail trim cover. | 09-24-2009 |
20090261601 | CARRIER AND FRONT END MODULE SYSTEM - A carrier for a front end module as a front structure of a vehicle, and a front end module system, comprises a sub frame formed to extend horizontally across an opening of a quadrangular main frame in which a radiator is to be arranged, and air guides are formed on the main frame and the sub frame to project forward. | 10-22-2009 |
20130147619 | METHOD OF DETERMINING FAILURE OF ACTIVE AIR FLAP - A method of determining a failure of an active air flap, including determining whether or not an active air flap is in a non-openable state, if the active air flap is in the non-openable state, continuously checking a variation of the temperature of engine-cooling water, and if the variation is below a reference variation, interrupting the generation of failure-alert, and if the variation of the temperature of engine-cooling water is above the reference variation, processing whether to generate the failure-alert such that if the time taken to reach the variation is above a reference temperature time, interrupting the generation of failure-alert, and if the time is below the reference temperature time, generating the failure-alert. | 06-13-2013 |
Patent application number | Description | Published |
20120043595 | CAPACITOR DEVICE AND METHOD OF FABRICATING THE SAME - A capacitor device includes a substrate including a first well having a first conductivity type and a first voltage applied thereto and a second well having a second conductivity type and a second voltage applied thereto; and a gate electrode disposed on an upper portion of the first well or an upper portion of the second well in such a way that the gate electrode is insulated from the first well or the second well, wherein capacitances of the capacitor device include a first capacitance between the first well and the second well and a second capacitance between the first well or the second well and the gate electrode. | 02-23-2012 |
20130001672 | SEMICONDUCTOR DEVICE - A semiconductor device includes a main active region provided in a semiconductor substrate and having a first side surface and a second side surface facing each other. A first auxiliary active region adjacent the first side surface of the main active region and spaced apart from the main active region by a first distance is provided. A second auxiliary active region adjacent the second side surface of the main active region and spaced apart from the main active region by the first distance is provided. A first conductive pattern crosses the main active region and includes first and second side portions facing each other. The first side portion of the conductive pattern is disposed between the first auxiliary active region and the main active region, and the second side portion of the conductive pattern is disposed between the second auxiliary active region and the main active region. | 01-03-2013 |
20130002294 | PROGRAMMABLE CIRCUIT - Provided is a programmable circuit. The programmable circuit includes a first path and a second path connected in parallel between a first voltage node and a second voltage node. The first path includes a first programmable element, a first node, a first pull-up transistor, a second node, and a first pull-down transistor connected in series between the first voltage node and the second voltage node. The second path includes a second programmable element, a third node, a second pull-up transistor, a fourth node, and a second pull-down transistor connected in series between the first and second voltage nodes. A gate electrode of the first pull-up transistor, a gate electrode of the first pull-down transistor, and the fourth node are electrically connected to one another. A gate electrode of the second pull-up transistor, a gate electrode of the second pull-down transistor, and the second node are electrically connected to one another. | 01-03-2013 |
Patent application number | Description | Published |
20130134697 | AIRBAG APPARATUS FOR VEHICLE - An airbag apparatus for a vehicle may include a vent hole formed on an airbag cushion to discharge an expanding gas inside of the airbag cushion, a cover attached on the outside of the airbag and selectively covering the vent hole, a rope, one end of which may be fixed to the inside of the airbag cushion and the other end of which may be fixed to the cover through the vent hole to provide a tensile force to the cover such that the cover opens or closes the vent hole according to the tensile force applied to the cover via the rope, and a rope-guide attached to the inside of the airbag cushion and upholding the rope to the airbag cushion, wherein the rope may be slidably engaged to the rope-guide and a section of the rope may be aligned longitudinally in the airbag cushion. | 05-30-2013 |
20130147171 | AIRBAG FOR VEHICLE - An airbag apparatus for a vehicle, may include an integrated vent formed in an airbag cushion, a tube provided on the airbag cushion and communicating with the integrated vent, wherein an inner diameter of the tube varies while gas may be discharged through the tube, so that a rate at which gas may be discharged from the airbag cushion may be adjusted according to a point of time of deployment of the airbag cushion, and a tether wrapped around the tube, the tether being connected to inner surface of the airbag cushion such that opposite ends of the tether may be pulled away from each other when the airbag cushion deploys, so that in a predetermined time period of the deployment of the airbag cushion, the tether contracts the tube, and after the predetermined time period, the tether snaps, thus releasing the tube. | 06-13-2013 |
20130307253 | AIRBAG COVER AND MODULE - An airbag cover includes a housing section which forms an upper part of which is opened and into which a folded airbag cushion is housed; and a guide section which is formed by extending an upper rear end and both ends of the opened housing section to form an additional space for extending a space of the housing section and a front surface of which at a passenger side is opened to guide an initial deployment direction of the airbag cushion toward a passenger side. | 11-21-2013 |
Patent application number | Description | Published |
20080224092 | Etchant for metal - An etchant for a metal is described. In one example, the etchant includes ammonium persulfate ((NH | 09-18-2008 |
20110226727 | ETCHANT FOR METAL WIRING AND METHOD FOR MANUFACTURING METAL WIRING USING THE SAME - Exemplary embodiments of the present invention provide a metal wiring etchant. A metal wiring etchant according to an exemplary embodiment of the present invention includes ammonium persulfate, an organic acid, an ammonium salt, a fluorine-containing compound, a glycol-based compound, and an azole-based compound. | 09-22-2011 |
20140011352 | METAL WIRE ETCHANT AND METHOD OF FORMING METAL WIRE USING THE SAME - A metal wire etchant including persulfate, a sulfonate, a fluorine compound, an azole-based compound, an organic acid, a nitrate, and a chlorine compound, and a method of making the same. | 01-09-2014 |
20140295626 | ETCHANT COMPOSITION, AND METHOD OF MANUFACTURING A DISPLAY SUBSTRATE USING THE SAME - An etchant composition includes about 25 percent by weight to about 35 percent by weight of phosphoric acid, about 3 percent by weight to about 9 percent by weight of nitric acid, about 10 percent by weight to about 20 percent by weight of acetic acid, about 5 percent by weight to about 10 percent by weight of a nitrate, about 6 percent by weight to about 15 percent by weight of a sulfonic acid, about 1 percent by weight to about 5 percent by weight of an amine compound including a carboxyl group, about 0.1 percent by weight to about 1 percent by weight of a water-soluble amino acid, about 0.01 percent by weight to about 1 percent by weight of an azole compound, and water. | 10-02-2014 |
20150087148 | ETCHANT COMPOSITION AND METHODS OF FABRICATING METAL WIRING AND THIN FILM TRANSISTOR SUBSTRATE USING THE SAME - An etchant composition including 0.5 wt % to 20 wt % of a persulfate, 0.01 wt % to 1 wt % of a fluorine compound, 1 wt % to 10 wt % of an inorganic acid, 0.01 wt % to 2 wt % of an azole-based compound, 0.1 wt % to 5 wt % of a chlorine compound, 0.05 wt % to 3 wt % of a copper salt, 0.01 wt % to 5 wt % of an antioxidant or a salt thereof, based on a total weight of the etchant composition, and water in an amount sufficient for the total weight of the etchant composition to be equal to 100 wt % is disclosed. The etchant composition is suitable for use in forming a metal wiring by etching a metal layer including copper or in fabricating a thin film transistor substrate for a display apparatus. | 03-26-2015 |
Patent application number | Description | Published |
20100167498 | SUBSTRATE LEVEL BONDING METHOD AND SUBSTRATE LEVEL PACKAGE - Disclosed are a substrate level bonding method and a substrate level package formed thereby. The substrate level package includes a plurality of unit substrate sections, a base substrate, and a plurality of substrate adhesion sections. The unit substrate sections are separated from each other by holes. The base substrate is disposed to face the unit substrate sections. The substrate adhesion sections are interposed between the unit substrate sections and the base substrate to bond the unit substrate sections to the base substrate and which are formed of DFR material, whose at least one portion is uncured. | 07-01-2010 |
20110021162 | SYSTEM FOR TRANSMITTING/RECEIVING MULTI-BAND RADIO FREQUENCY SIGNAL USING DUAL INPUT, DUAL OUTPUT FILTER - A system for transmitting/receiving a multi-band Radio Frequency (RF) signal using a Dual Input, Dual Output filter is provided. The system may include a Single-Input Single-Output (SISO) filter and the Dual Input, Dual Output filter. The system for transmitting/receiving a multi-band Radio Frequency (RF) may be implemented in a Radio Frequency (RF) region, which includes an area from an end of an antenna to an end of a mixer in a mobile communication. | 01-27-2011 |
20130033340 | BULK ACOUSTIC WAVE RESONATOR - Provided is a bulk acoustic wave resonator (BAWR). The BAWR may include a bulk acoustic wave resonance unit and an anti-resonant frequency modifying unit to modify an anti-resonant frequency generated from the bulk acoustic wave resonance unit. | 02-07-2013 |
20130248368 | SENSING APPARATUS USING RADIO FREQUENCY AND MANUFACTURING METHOD THEREOF - A sensing apparatus using a radio frequency and a manufacturing method thereof is provided. A sensing apparatus using a radio frequency includes a protecting layer configured to protect a substrate from migration of electrons occurring as the radio frequency is applied to a first electrode and a second electrode, a channel forming layer configured to form a channel based on a field between the first electrode and the second electrode, the channel forming layer using a polarized carbon-based nano material to form the channel, and a sensing layer configured to sense glucose using a medium material that is attached on the carbon-based nano material. | 09-26-2013 |
20140110763 | NANO RESONANCE APPARATUS AND METHOD - A nano resonance apparatus includes a gate electrode configured to generate a magnetic field, and a nanowire connecting a source electrode to a drain electrode and configured to vibrate in the presence of the magnetic field. The nanowire includes a protruding portion extending in a direction of the gate electrode. | 04-24-2014 |
20140203686 | RESONATOR AND FABRICATING METHOD THEREOF - Provided are a resonator and a method of fabricating the same. The resonator may include a first electrode disposed on a substrate, a piezoelectric layer disposed on the first electrode, a second electrode disposed on the piezoelectric layer, and a control layer disposed on the second electrode and having a frame with an uneven surface. | 07-24-2014 |
Patent application number | Description | Published |
20100062559 | Methods of manufacturing image sensors having shielding members - An epitaxial layer may be formed on a substrate having a first region and a second region. A photo diode may be formed on a first portion of the epitaxial layer in the first region of the substrate. At least one transfer transistor may be formed on the epitaxial layer adjacent to the photo diode. A plurality of transistors may be formed on a second portion of the epitaxial layer in the second region. An insulation layer may be formed to cover the photo diode, the at least one transfer transistor and the plurality of transistors. A plurality of connections may be formed through the insulation layer to be electrically connected with the at least one transfer transistor and the plurality of transistors in the second region. A shielding member may be formed to expose the photo diode. The epitaxial layer and/or the substrate may be treated with a hydrogen plasma before forming the shielding member to remove dangling bonds of silicon-oxygen and/or silicon-silicon. | 03-11-2010 |
20120077301 | IMAGE SENSOR AND METHOD OF FABRICATING THE SAME - An image sensor and a method for fabricating the image sensor are provided. The method for fabricating the image sensor includes forming a first insulating layer on a semiconductor epitaxial layer having multiple pixel regions; patterning a portion of the semiconductor epitaxial layer and the first insulating layer in a boundary region between the pixel regions to form a trench; forming a buried insulating layer on the first insulating layer, filling the trench, the buried insulating layer having a planar top surface; forming a second insulating layer on the buried insulating layer; forming a first mask pattern on the second insulating layer, the first mask pattern defining an opening overlapping the trench; and performing an ion implantation process using the first mask pattern as an ion implantation mask to form a first type potential barrier region in a bottom of the trench. | 03-29-2012 |
20120199882 | Image Sensors Including A Gate Electrode Surrounding A Floating Diffusion Region - Image sensors are provided. The image sensors may include first and second stacked impurity regions having different conductivity types. The image sensors may also include a floating diffusion region in the first impurity region. The image sensors may further include a transfer gate electrode surrounding the floating diffusion region in the first impurity region. Also, the transfer gate electrode and the floating diffusion region may overlap the second impurity region. | 08-09-2012 |
20120252155 | METHOD OF IMPLANTING IMPURITIES AND METHOD OF MANUFACTURING A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) IMAGE SENSOR USING THE SAME - In a method of doping impurities, an amorphous layer is formed on a substrate. Impurities are implanted through a top surface of the amorphous layer to form a first doping region at an upper portion of the substrate. The first doping region and the amorphous layer are transformed into a second doping region and a recrystallized layer, respectively, by a laser annealing process. The recrystallized layer is removed. | 10-04-2012 |
Patent application number | Description | Published |
20110231467 | MONTGOMERY MULTIPLIER HAVING EFFICIENT HARDWARE STRUCTURE - A radix-2k Montgomery multiplier including an input coefficient generation unit to receive a multiplier, a multiplicand, a modulus, a sum and a previous sum, to generate and to output a partial product and a multiple modulus by using at least one of the multiplier, the multiplicand, the modulus and the sum, and to divide and to output the received previous sum into units of k bits, an accumulator circuit to receive the partial product, the multiple modulus and k bits of the previous sum from the input coefficient generation unit, and to generate and to output a carry and a sum by summing the partial product, the multiple modulus and the previous sum, and a carry propagation adder (CPA) circuit to generate and to output an ultimate sum by using the carry and the sum. | 09-22-2011 |
20120096062 | MODULAR CALCULATOR, OPERATION METHOD OF THE MODULAR CALCULATOR, AND APPARATUSES HAVING THE SAME - A modular calculator and a method of performing a modular calculation are provided. The modular calculator includes a first register to receive and to store a first integer, a second register to receive and to store a second integer, a calculator connected to an output terminal of the first register and an output terminal of the second register, and a controller to determine an arithmetic operation of the calculator by referring to a sign of the first integer and a sign of the second integer and to control the calculator to perform the determined arithmetic operation on one of an addition and a subtraction of the first integer and the second integer and a modulus value. | 04-19-2012 |
20120197953 | MONTGOMERY INVERSE CALCULATION DEVICE AND METHOD OF CALCULATING MONTGOMERY INVERSE USING THE SAME - A Montgomery inverse calculation device includes a plurality of registers each storing a value of a variable, a modulus register storing a modulus, a multiplier performing multiplication on the modulus. A comparator compares the value of the variable stored in each of the registers with an output value of the multiplier and generates a plurality of control signals. A plurality of shifters shifts bits of a value of a variable stored in a corresponding register among the registers in response to at least one first control signal, and a quotient generation block calculates a quotient of mod 2m with respect to values output from some of the shifters in response to a second control signal. A calculation block calculates an updated value of an output value of each of the shifters using the quotient in response to at least one third control signal. | 08-02-2012 |
20120317159 | MODULAR OPERATOR, DEVICE HAVING THE SAME, AND OPERATING METHOD THEREOF - A modular operator, a smart card including the same, and a method of operating the same are provided. The modular operator includes: an input unit configured to receive first data, second data, and a modulus; and an accumulator configured to perform an accumulation operation on the first data and a first portion of the second data, to shift the accumulation operation result to the right as much as the number of bits of the first portion, and to perform an accumulation operation on a result of a shifted accumulation operation, a second part, of the second data, which is shifted to the right as much as the number of bits of the first portion, and the modulus. | 12-13-2012 |
20120319561 | FIELD EMISSION PANEL, LIQUID CRYSTAL DISPLAY AND FIELD EMISSION DISPLAY HAVING THE SAME - A field emission panel, a liquid crystal display and a field emission display having the same are provided. The field emission panel includes a lower plate emitting electrons and an upper plate generating white light or a color image through collision with the electrons. The lower plate includes plural field emission elements, plural cathode electrodes and plural gate electrodes forming an electric field for electron emission from the electron emission elements, and a glass plate supporting the electron emission elements, the cathode electrodes, and the gate electrodes. The gate electrodes are arranged on an upper surface of the glass plate, and the glass plate has plural accommodation grooves for accommodating the plural electron emission elements and the plural cathode electrodes. | 12-20-2012 |
20130259224 | METHOD OF GENERATING A RANDOM PERMUTATION, RANDOM PERMUTATION GENERATING DEVICE, AND ENCRYPTION/DECRYPTION DEVICE HAVING THE SAME - Generating a random permutation by arranging a sequence N numbers in a matrix, performing random arrangement operations on the rows of the matrix to generate an intermediary matrix, performing random arrangement operations on the columns of the intermediary matrix to generate a second intermediary matrix, and arranging the N numbers of the second intermediary matrix as a rearranged sequence of the N numbers. | 10-03-2013 |
20130262544 | ELECTRONIC MULTIPLIER AND DIGITAL SIGNAL PROCESSOR INCLUDING THE SAME - An electronic multiplier, such as a multiplication circuit, may include a partial product generator, a Booth code encoder and an accumulator. The partial product generator may generate partial product data based on a Booth code and multiplicand data. The Booth code encoder may generate the Booth code based on multiplier data. The Booth code may include a zero-generation Booth code and a zero-avoidance Booth code. The Booth code encoder may selectively generate the zero-generation Booth code or the zero-avoidance Booth code when the partial product data correspond to a partial product of zero. The accumulator accumulates the partial product data to provide a multiplication result of the multiplicand data and the multiplier data. | 10-03-2013 |
Patent application number | Description | Published |
20110134071 | DISPLAY APPARATUS AND TOUCH SENSING METHOD - A display apparatus and a touch sensing method are provided. The display apparatus includes a touch screen which senses a touch by a user using a plurality of sensing types; and a controller which selects a sensing type based on an application. Therefore, a user's touch is sensed using an optimal sensing type for each application. In doing so, malfunction or inconvenience in manipulating the touch screen can be reduced. | 06-09-2011 |
20120147269 | IMAGE PROCESSING APPARATUS, USER TERMINAL APPARATUS, IMAGE PROCESSING METHOD, AND CONTROL METHOD THEREOF - An image processing apparatus includes an image processing unit which processes an image signal, a display unit which displays the processed image, a user interface unit which receives a user command to capture an image, a screen capture unit which captures an image frame according to the user command, a storage unit which stores the image frame captured by the screen capture unit, and a control unit which controls the screen capture unit to capture a plurality of image frames including the image frame corresponding to a point of time when the user command is input. | 06-14-2012 |
20120180090 | METHOD FOR DISPLAYING VIDEO AND BROADCAST RECEIVING APPARATUS APPLYING THE SAME - A method for displaying video and a broadcast receiving apparatus applying the same. The broadcast receiving apparatus includes an output unit which outputs a user interface window containing a plurality of groups having at least one broadcast channel, an input unit which receives a zapping command, a receiving unit which is tuned to a broadcast channel and receives a broadcast signal, and a control unit which controls the receiving unit, if one from among the plurality of groups categorized according to at least one criterion of categorization is selected and the zapping command is inputted, so that the receiving unit is tuned to the broadcast channels belonging to the selected group in sequence. | 07-12-2012 |
20140047474 | IMAGE PROCESSING APPARATUS AND CONTROL METHOD THEREOF - An image processing apparatus including: a connector which receives a signal in at least one external input; a signal processor which processes the signal received, and displays an image on a display unit based on the processed signal; and a controller which displays a guide image which guides a user to connect the at least one external input to the connector, sequentially displays on the display unit a setting image of the at least one external input to sequentially perform a connection setting for the connector to receive the signal in the at least one external input after the guide image is displayed, detects a signal input characteristic of a first external input of the at least one external input connected to the connector after the guide image is displayed, and selectively displays the setting image corresponding to the first external input according to the detection result. | 02-13-2014 |
20140223321 | PORTABLE DEVICE AND METHOD FOR CONTROLLING EXTERNAL DEVICE THEREOF - A method for controlling a portable device and an external device thereof is provided. When a preset user command is input while a portable device is in a lock mode, the portable device displays a remote control UI which controls an external device, and performs pairing with the external device based on the remote control UI to control the external device. | 08-07-2014 |
20150039308 | APPARATUS, SERVER, AND METHOD FOR PROVIDING CONVERSATION TOPIC - A conversation topic providing method includes: converting voice data, of a conversation of a user who is on a phone, into text; selecting a keyword, indicating an intention of the user, from the text; obtaining information of interest with respect to the keyword; and determining topics relating to the keyword based on user information. | 02-05-2015 |
Patent application number | Description | Published |
20100271327 | DISPLAY PANEL, DISPLAY APPARATUS HAVING THE SAME AND METHOD OF DRIVING THE DISPLAY APPARATUS - In a display panel, a display apparatus having the display panel, and a method of driving the display apparatus, a conductive spacer is interposed between an array substrate and an opposite substrate, and the conductive spacer electrically connects a pixel electrode and a common electrode when a touch event occurs for one or more embodiments. When a common voltage is applied to the pixel electrode by the touch event, an electric potential of a data line is lowered by the common voltage through a turned-on switching device. A signal reader periodically reads out the voltage of the data line and senses the touch event using the read-out voltage to detect a touch position at which the touch event occurs. Thus, the display panel having a touch screen function may be manufactured, and an aperture ratio in the display panel may be prevented from being deteriorated. | 10-28-2010 |
20110216259 | DISPLAY PANEL - A display panel includes a first substrate, a second substrate facing the first substrate, and a liquid crystal layer. The first substrate includes a plurality of pixels, each having at least one gray scale expression unit to express at least two gray scales. The liquid crystal layer is interposed between the first and second substrates and subject to a phase transition depending on a voltage generated in relation to the gray scale expression unit. The gray scale expression unit includes a data line, a gate line crossing the data line and insulated from the data line, a switching device connected to the data line and the gate line, a first pixel electrode connected to the switching device, at least one coupling capacitor connected to the first pixel electrode in parallel, and at least one second pixel electrode connected to the first pixel electrode in parallel through the coupling capacitor. | 09-08-2011 |
20110261307 | LIQUID CRYSTAL DISPLAY - In a liquid crystal display, a first alignment layer formed on a first substrate includes a first region aligned in a first direction and a second region aligned in a second direction opposite to the first direction, and a second alignment layer formed on a second substrate facing the first substrate includes a third region aligned in a third direction different from the first direction and a fourth region aligned in a fourth direction opposite to the third direction. The liquid crystal molecules interposed between the first and second alignment layers are aligned in different directions in different domains defined by the first to fourth regions. A pixel electrode includes an extension part extending in at least one of the first to fourth directions. The aperture ratio and the light transmittance of the liquid crystal display are improved. | 10-27-2011 |
20120154727 | LIQUID CRYSTAL DISPLAY PANEL - A liquid crystal display panel including pixels, wherein at least one of the pixels includes a first sub-pixel charged with a first voltage and a second sub-pixel charged with a second voltage lower than the first voltage, a first substrate including a first sub-pixel electrode of the first sub-pixel and a second sub-pixel electrode of the second sub-pixel, a first alignment layer aligned in first and second directions in each of the first and second sub-pixels, a second alignment layer aligned in third and fourth directions in each of the first and second sub-pixels to form a plurality of domains in each of the first and second sub-pixels, and a liquid crystal layer disposed between the first and second alignment layers, wherein the first sub-pixel electrode includes a plurality of slits formed substantially parallel to a liquid crystal alignment direction in each of the domains of the first sub-pixel electrode. | 06-21-2012 |
20120274885 | IMAGE DISPLAY APPARATUS INCLUDING PIXEL ELETRODES WITH OPENINGS - In an image display apparatus, an array substrate includes a plurality of pixel electrodes, an opposite substrate facing the array substrate, and a liquid crystal layer disposed between the array substrate and the opposite substrate. The liquid crystal layer includes a plurality of vertical alignment liquid crystal molecules and is disposed between the array substrate and the opposite substrate. Each of the pixel electrodes includes a plurality of domains and includes an opening portion formed corresponding to a contact point at which the domains make contact with each other. | 11-01-2012 |
20120293736 | DISPLAY APPARATUS - A display apparatus includes a plurality of pixels. At least one of the pixels includes a gate line, a data line, a first storage line spaced apart from the gate line, a second storage line spaced apart from the gate line and the first storage line, first and second switching devices electrically connected to the gate line and the data line, a first liquid crystal capacitor connected to the first switching device and including the liquid crystal layer as its dielectric substance, a second liquid crystal capacitor connected to the second switching device and including the liquid crystal layer as its dielectric substance, a first storage capacitor connected between the first switching device and one of the first and second storage lines, and a second storage capacitor connected between the second switching device and a remaining one of the first and second storage lines. | 11-22-2012 |
20130088532 | DISPLAY DEVICE FOR DISPLAYING PLANAR IMAGE AND THREE DIMENSIONAL IMAGE - A display device includes a gray scale voltage generating unit configured to generate at least one gray scale voltage set, a timing control unit configured to convert an externally input image signal into a predetermined format to output a converted image signal, a data driving unit configured to convert the converted image signal into a data voltage based on the at least one gray scale voltage set, and a display panel configured to control a plurality of sub pixels based on the data voltage, where the display panel controls the plurality of sub pixels using one gamma setting when the externally input image signal is a three-dimensional image signal, and controls the plurality of sub pixels using different gamma settings when the externally input image signal is a planar image signal. | 04-11-2013 |
20140184653 | IMAGE PROCESSING DEVICE AND DISPLAY DEVICE HAVING THE SAME - An image processing device includes a first filter that filters the image signal to output a first image signal, a second filter that converts the image signal corresponding to a predetermined pixel to a second image signal based on image signals corresponding to a plurality of peripheral pixels adjacent to the predetermined pixel, a third filter that filters the second image signal from the second filter to output a third image signal, a fourth filter that filters the third image signal from the third filter to output a fourth image signal, and an image synthesizer that synthesizes the first image signal from the first filter and the fourth image signal from the fourth filter. | 07-03-2014 |
Patent application number | Description | Published |
20120312652 | METHOD OF CONTROLLING TRANSMISSION OF VEHICLE - A method of controlling a transmission of a vehicle may include generating a first synchronization force between a shift gear of a target gear and an output shaft to shift gears from a current gear to a lower gear set as the target gear in response to deceleration of the vehicle, so as to form a first synchronization, removing the first synchronization force between the shift gear and the output shaft after the generating of the first synchronization force, and generating a second synchronization force between the shift gear of the target gear and the output shaft after the removing of the first synchronization force, so as to form a second synchronization. | 12-13-2012 |
20120312653 | METHOD OF CONTROLLING TRANSMISSION OF VEHICLE - A method of controlling a transmission of a vehicle may include beginning synchronization between a speed shift gear of a target gear and an output shaft to shift gears from a current gear to a lower gear set as the target gear in response to deceleration of the vehicle, after the synchronization between the output shaft and an input shaft by the speed shift gear of the target gear has been completed, maintaining the synchronized state therebetween for a predetermined time period, and completing engagement with the target gear to complete the shifting of the gears after the maintaining of the synchronized state. | 12-13-2012 |
20140041478 | DAMPER FOR INPUT SHAFT OF TRANSMISSION - A damper apparatus for an input shaft of a transmission, may include a flywheel having a reception space in which a inertial body may be provided so as to be rotatable relative to the flywheel, the input shaft extending into the reception space of the flywheel, and an inertial body assembly slidably coupled to the input shaft so as to provide rotational inertial force to the input shaft, the inertial body assembly being disposed in the reception space. | 02-13-2014 |
20140045646 | APPARATUS FOR DAMPING FLYWHEEL - An apparatus for damping a flywheel includes a drive plate integrally connected to a crankshaft A flywheel is connected to receive a rotating force from the drive plate through planetary gearing, and is mounted to rotate relative to the crankshaft. A rigidity imparting means is disposed on a path along which a rotating force is transferred between the drive plate and the flywheel. A mass body is provided on the flywheel, and is configured to perform relative rotation in a direction that offsets a torsional vibration of an engine transmitted to the flywheel. | 02-13-2014 |
Patent application number | Description | Published |
20120139090 | STACKED PACKAGE STRUCTURE - A stacked package structure is provided. The stacked package structure includes a stacked package including a lower semiconductor package, an upper semiconductor package disposed on the lower semiconductor package and spaced a predetermined distance apart from the lower semiconductor package, an inter-package connecting portion electrically connecting the lower semiconductor package and the upper semiconductor package while supporting a space therebetween, and an insulation layer disposed at least outside the inter-package connecting portion and filling the space between the lower semiconductor package and the upper semiconductor package, and an electromagnetic shielding layer surrounding lateral and top surfaces of the stacked package. | 06-07-2012 |
20130256917 | SEMICONDUCTOR PACKAGES - A semiconductor package includes a master chip and a slave chip stacked on a substrate. The master chip and the slave chip are connected to one another by a bonding wire. The master chip and the slave chip are connected in series with an external circuit. The semiconductor package may have a low loading factor and excellent performance, and may be mass produced at low costs. | 10-03-2013 |
20140264339 | HEAT SLUG HAVING THERMOELECTRIC ELEMENTS AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - In a heat slug and a semiconductor package including the same, the heat slug includes a thermal conductive body having an active face and a dissipating face opposite to the active face, a dielectric layer covering the active face of the body, at least one thermoelectric element arranged on the dielectric layer and a conductive pattern arranged on the dielectric layer and electrically connected to the thermoelectric element. The electrical characteristics of the thermoelectric element are interacted with heat generated from a heat source. | 09-18-2014 |
20140328023 | SEMICONDUCTOR PACKAGE HAVING EMI SHIELDING FUNCTION AND HEAT DISSIPATION FUNCTION - A semiconductor package includes a substrate, a semiconductor chip located on a top surface of the substrate, signal lines formed on the top surface of the substrate and configured to allow different types of signals to input/output thereto/therefrom, a ground line unit formed on the top surface of the substrate and configured to divide the signal lines into signal lines to/from which the same types of signals are input/output to be isolated from one another, barrier walls configured to contact the ground line unit, and a heat dissipation unit disposed on the semiconductor chip, wherein the ground line unit includes diagonal ground lines located in diagonal directions of the substrate about the semiconductor chip, and the heat dissipation unit includes a thermal interface material (TIM) located on a top surface of the semiconductor chip, and a heat dissipation plate configured to cover the TIM and the substrate. | 11-06-2014 |
20140339692 | SEMICONDUCTOR PACKAGE STACK HAVING A HEAT SLUG - A semiconductor package stack, comprising: a lower semiconductor package including a lower semiconductor chip mounted on a lower package board; an upper semiconductor package stacked on the lower semiconductor package and including an upper semiconductor chip mounted on an upper package board, wherein the upper package board includes an opening configured to expose a lower surface of the upper semiconductor chip; and a first heat slug disposed within the opening, contacting the lower surface of the upper semiconductor chip, and contacting an upper surface of the lower semiconductor chip. | 11-20-2014 |
20140362551 | PRINTED CIRCUIT BOARD INCLUDING INDUCTOR - A printed circuit board (PCB) includes an insulating substrate, a plurality of copper foil pattern layers and a plurality of insulating adhesive sheets sequentially stacked on an upper side of the insulating substrate and a lower side of the insulating substrate, an inductor included in the copper foil pattern layer disposed on the upper side of the insulating substrate, a grounding element included in the copper foil pattern layer disposed on the lower side of the insulating substrate, and a single through hole penetrating the insulating substrate and the insulating adhesive sheets. The single through hole is disposed between the inductor and the grounding element. | 12-11-2014 |
20150024545 | STACKED PACKAGE STRUCTURE AND METHOD OF MANUFACTURING A PACKAGE-ON-PACKAGE DEVICE - A stacked package structure is provided. The stacked package structure includes a stacked package including a lower semiconductor package, an upper semiconductor package disposed on the lower semiconductor package and spaced a predetermined distance apart from the lower semiconductor package, an inter-package connecting portion electrically connecting the lower semiconductor package and the upper semiconductor package while supporting a space therebetween, and an insulation layer disposed at least outside the inter-package connecting portion and filling the space between the lower semiconductor package and the upper semiconductor package, and an electromagnetic shielding layer surrounding lateral and top surfaces of the stacked package. | 01-22-2015 |
Patent application number | Description | Published |
20110167427 | COMPUTING SYSTEM, METHOD AND COMPUTER-READABLE MEDIUM PREVENTING STARVATION - A computing system, method and computer-readable medium is provided. To prevent a starvation phenomenon from occurring in a priority-based task scheduling, a plurality of tasks may be divided into a priority-based group and other groups. The groups to which the tasks belong may be changed. | 07-07-2011 |
20110173622 | System and method for dynamic task migration on multiprocessor system - A multiprocessor system and a migration method of the multiprocessor system are provided. The multiprocessor system may process dynamic data and static data of a task to be operated in another memory or another processor without converting pointers, in a distributed memory environment and in a multiprocessor environment having a local memory, so that dynamic task migration may be realized. | 07-14-2011 |
20110173633 | Task migration system and method thereof - A task migration system is provided which transmits a migration request signal for a plurality of first tasks to a migration manager using a resource manager, transmits information used in response to the migration request signal from a migration initiation handler to the migration manager when a first task, of which a migration point is in a capture ready state, among the plurality of first tasks is received from a processor, and captures, using the migration manager, the migration point of the first task in the capture ready state, in response to a migration request signal for the first task in the capture ready state, so that the first task with the captured migration point migrates to a second task. | 07-14-2011 |
20120005679 | APPARATUS AND METHOD FOR THREAD PROGRESS TRACKING USING DETERMINISTIC PROGRESS INDEX - Provided is a method and apparatus for measuring a performance or a progress state of an application program to perform data processing and execute particular functions in a computing environment using a micro architecture. A thread progress tracking apparatus may include a selector to select at least one thread constituting an application program; a determination unit to determine, based on a predetermined criterion, whether an instruction execution scheme corresponds to a deterministic execution scheme having a regular cycle or a nondeterministic execution scheme having an irregular delay cycle with respect to each of at least one instruction constituting a corresponding thread; and a deterministic progress counter to generate a deterministic progress index with respect to an instruction that is executed by the deterministic execution scheme, excluding an instruction that is executed by the nondeterministic execution scheme. | 01-05-2012 |
20120023505 | APPARATUS AND METHOD FOR THREAD SCHEDULING AND LOCK ACQUISITION ORDER CONTROL BASED ON DETERMINISTIC PROGRESS INDEX - Provided is a method and apparatus for ensuring a deterministic execution characteristic of an application program to perform data processing and execute particular functions in a computing environment using a micro architecture. A lock controlling apparatus based on a deterministic progress index (DPI) may include a loading unit to load a DPI of a first core and a DPI of a second core among DPIs of a plurality of cores at a lock acquisition point in time of each thread, a comparison unit to compare the DPI of the first core and the DPI of the second core, and a controller to assign a lock to a thread of the first core when the DPI of the first core is less than the DPI of the second core and when the second core corresponds to a last core to be compared among the plurality of cores. | 01-26-2012 |
20120198182 | MULTI-CORE SYSTEM AND METHOD FOR PROCESSING DATA IN PARALLEL IN MULTI-CORE SYSTEM - A multi-core system and a method for processing data in parallel in the multi-core system are provided. In the multi-core system, partitioning and allocating of data may be dynamically controlled based on local memory information. Thus, it is possible to increase an availability of a Central Processing Unit (CPU) and a local memory, and is possible to improve a performance of data parallel processing. | 08-02-2012 |
20130097613 | APPARTUS AND METHOD FOR THREAD PROGRESS TRACKING - Provided is a method and apparatus for measuring a progress or a performance of an application program in a computing environment using a micro-architecture. An apparatus for thread progress tracking may select a thread included in an application program, may determine, based on a predetermined criterion, whether an execution scheme for at least one instruction included in the thread corresponds to an effective execution scheme in which an execution time is uniform or a non-effective execution scheme in which a delayed cycle is included and the execution time is non-uniform, and may generate an effective progress index (EPI) by accumulating an execution time of an instruction executed by the effective execution scheme other than an instruction executed by the non-effective execution scheme. | 04-18-2013 |
20130111472 | VIRTUAL ARCHITECTURE GENERATING APPARATUS AND METHOD, AND RUNTIME SYSTEM, MULTI-CORE SYSTEM AND METHODS OF OPERATING RUNTIME SYSTEM AND MULTI-CORE SYSTEM | 05-02-2013 |
20130342528 | APPARATUS AND METHOD FOR TRAVERSING HIERARCHICAL ACCELERATION STRUCTURE - An apparatus and method for traversing a hierarchical acceleration structure may determine whether a current traversal node is a leaf node, may calculate a first distance from the current traversal node to a pop level and a second distance from a root node to the pop level when the current traversal node is the leaf node, and may determine a hierarchical traversal restarting position by comparing the first distance and the second distance. | 12-26-2013 |
20140019782 | APPARATUS AND METHOD FOR MANAGING POWER BASED ON DATA - Provided is an apparatus and method for managing power based on data. The apparatus may include a code segment searching unit configured to search for at least one code segment in which a power type is inserted, a block determining unit configured to determine at least one block based on the at least one found code segment, and a power mode control unit configured to control the at least one determined block to operate in a power mode corresponding to the power type. | 01-16-2014 |
20140032976 | APPARATUS AND METHOD FOR DETECTING ERROR - An apparatus and method for detecting an error occurring when an application program is executed in a computer environment is provided. The error detection apparatus may measure a deterministic progress index (DPI) and a program counter (PC) value when an instruction is executed, set, as a verification set, a DPI and a PC value measured when the instruction is executed without causing an error, set, as a measurement set, the DPI and the PC value measured when an instruction is executed, and detect a runtime error of the instruction by comparing the measurement set to the verification set. | 01-30-2014 |
20140049539 | METHOD AND APPARATUS FOR GRAPHIC PROCESSING USING PARALLEL PIPELINE - An apparatus and method for ray tracing includes a traversal (TRV) unit using a tree acceleration structure (AS). The TRV unit may include a plurality of sub-pipeline units configured to perform different operations required for ray TRV using the tree AS and to operate in parallel. | 02-20-2014 |
20140078143 | APPARATUS AND METHOD FOR SCHEDULING OF RAY TRACING - A graphic processing apparatus and method for processing ray tracing may include a plurality of traversal units to process traversal of a ray. A management unit of the graphics processing apparatus may distribute data of the ray processed by the graphics processing apparatus to the plurality of traversal units. Each of the plurality of traversal units may process ray traversal with respect to a subdivision of the entire space. | 03-20-2014 |
20140104271 | APPARATUS AND METHOD FOR IMAGE PROCESSING - A method for processing a three-dimensional (3D) image of a ray tracing scheme may be performed by an image processing apparatus by verifying whether local index information matching intersection point information of a ray is present within a prefetch table when intersection point information is received, and by transferring, to a shader, rendering information stored in a local memory based on the local index information, when the local index information matching the intersection point information is present. | 04-17-2014 |
20140244693 | METHOD AND APPARATUS FOR STACK MANAGEMENT - A method and apparatus for managing a stack used for a tree traversal (TRV) may include a processing unit that may manage a short stack for a tree TRV, and a storage unit that may store data of the short stack. The processing unit may perform a restart of the tree TRV from an intermediate node of a tree to fill the short stack when the short stack is empty. | 08-28-2014 |
20150026408 | CACHE MEMORY SYSTEM AND METHOD OF OPERATING THE SAME - A cache memory system and a method of operating the cache memory system are provided. The cache memory system includes: an address buffer for receiving address bits including a cache address and a tag address from the outside or externally; a cache memory including a memory array, the cache memory outputting, from a row of the memory array which the cache address designates, a plurality of pieces of tag data and a plurality of pieces of cache data corresponding to the plurality of pieces of tag data; and a register configured to temporarily store a data set including the plurality of pieces of cache data output from the cache memory. | 01-22-2015 |
20150084957 | METHOD AND APPARATUS FOR ROUTING DATA AND RECONFIGURING RENDERING UNIT - Provided are method and apparatuses for routing and reconfiguring rendering data, the method for routing including identifying, at a processor, a group of input data, transmitting the input data based on a routing path designated for the identified group, and updating the routing path based on a feedback signal regarding the transmitted data. The method for reconfiguring rendering units including measuring, at a processor, workloads of the rendering units used in rendering a previous frame, and reconfiguring the rendering units during rendering a current frame based on the workloads. | 03-26-2015 |