Patent application number | Description | Published |
20100243738 | PROCESSING APPARATUS OF PORTABLE ELECTRONIC DEVICES, PORTABLE ELECTRONIC DEVICE, AND PROCESSING SYSTEM OF PORTABLE ELECTRONIC DEVICES - A processing apparatus of portable electronic devices, a portable electronic device, and a processing system of portable electronic devices are provided, each of which can process data at high speed. The processing apparatus has a transmitting/receiving unit configured to transmit and receive data to and from the portable electronic device. In the processing, the transmitting/receiving unit generates a first command and adds a second command to the first command. | 09-30-2010 |
20110012714 | PROCESSING SYSTEM FOR PORTABLE ELECTRONIC APPARATUS, PORTABLE ELECTRONIC APPARATUS, AND PROCESSING APPARATUS FOR PORTABLE ELECTRONIC APPARATUS - A portable electronic apparatus has a first storage section configured to store information to be communicated to the processing apparatus and formats for a frame to be transmitted to the processing apparatus, in association with one another. The processing apparatus has a second storage section configured to store information communicated by the portable electronic apparatus and the format of the frame transmitted by the portable electronic apparatus, in association with each other. The portable electronic apparatus select one of the formats stored in the first storage section based on the data to be transmitted to the processing apparatus. The processing apparatus recognize information communicated by the portable electronic apparatus based on the format of the frame received from the portable electronic apparatus. | 01-20-2011 |
20110063080 | MOBILE ELECTRONIC DEVICE - According to one embodiment, a mobile electronic device that makes an initial response in a slot marker system, includes a reception unit configured to receive an initial response command from a terminal, a recognition unit configured to recognize a total slot number N (integer equal to or greater than 2) set in the terminal, from the initial response command received by the reception unit, a logic unit configured to generate an integer n from a random number, a storage unit configured to store data set to the mobile electronic device and representing whether the mobile electronic device is a main device or a sub device, and a control unit configured to cause the logic unit to generate 0 as integer n, thereby responding to the initial response command for the first time, if the mobile electronic device is set as the main device. | 03-17-2011 |
Patent application number | Description | Published |
20080285889 | IMAGE TRANSFORM METHOD FOR OBTAINING EXPANDED IMAGE DATA, IMAGE PROCESSING APPARATUS AND IMAGE DISPLAY DEVICE THEREFORE - It is an object of the present invention to output a clear, expanded image wherein step-shapes or chain-shapes of oblique lines are reduced, distortion is eliminated and no constituent lines of fonts or graphics are missing. An image transform method, for transforming original input image data into image data expanded by a ratio represented by a rational number or an integer, comprises: a vertical and horizontal interpolation unit, for reducing correlation in the vertical and horizontal directions of interpolated image data linearly expanded from an original image data input unit, and for generating first expanded image data; an oblique interpolation unit, for performing linear interpolation, based on correlation with a target pixel constituting the original image data and neighboring pixels arranged in oblique directions, using the neighboring pixels to generate second expanded image data; and a final result generator for employing the first expanded image data and the second expanded image data to generate a final image. | 11-20-2008 |
20110150364 | IMAGE TRANSFORM METHOD FOR OBTAINING EXPANDED IMAGE DATA, IMAGE PROCESSING APPARATUS AND IMAGE DISPLAY DEVICE THEREFOR - It is an object of the present invention to output a clear, expanded image wherein step-shapes or chain-shapes of oblique lines are reduced, distortion is eliminated and no constituent lines of fonts or graphics are missing. An image transform method, for transforming original input image data into image data expanded by a ratio represented by a rational number or an integer, comprises: a vertical and horizontal interpolation unit, for reducing correlation in the vertical and horizontal directions of interpolated image data linearly expanded from an original image data input unit, and for generating first expanded image data; an oblique interpolation unit, for performing linear interpolation, based on correlation with a target pixel constituting the original image data and neighboring pixels arranged in oblique directions, using the neighboring pixels to generate second expanded image data; and a final result generator for employing the first expanded image data and the second expanded image data to generate a final image. | 06-23-2011 |
Patent application number | Description | Published |
20090233323 | METHOD FOR ANALYSIS OF NKT CELL FUNCTION - The present invention provides a superior method of functional analysis of NKT cells, which enables function analysis of low frequency NKT cells, is independent of the function of autologous APCs, and can avoid an influence of secondary factors and the like. More specifically, the present invention provides a method of functional analysis of human NKT cells including (a) cocultivating a mononuclear cell derived from human peripheral blood with a CD1d-expressing antigen presenting cell derived from a heterologous animal, and (b) evaluating the functionality of NKT cells with the number of NKT cells and/or a substance specific to functional NKT cells as an index; a reagent for analysis of human NKT cells containing a CD1d-expressing antigen presenting cell derived from a heterologous animal; a kit containing (a) a CD1d-expressing antigen presenting cell derived from a heterologous animal, and (b) at least one reagent selected from the group consisting of a reagent for selection of human mononuclear cell, a reagent for measurement of the number of human NKT cells and a reagent for measurement of a substance specific to human functional NKT cells; and the like. | 09-17-2009 |
20100233215 | IMMUNOTHERAPY BY USING CELL CAPABLE OF CO-EXPRESSING TARGET ANTIGEN AND CD1d AND PULSED WITH CD1d LIGAND - The present invention provides a novel immunity induction method, particularly, a method of simultaneously inducing activation of NKT cells and T-cell immune responses. To be more precise, the present invention provides a target antigen and CD1d co-expressing cell, and a preparation and identification method thereof; a target antigen and CD1d co-expressing cell capable of activating immunity to the target antigen, and a preparation method thereof; an immunoinducer to a target antigen or a pharmaceutical agent, which contains a target antigen and CD1d co-expressing cell capable of activating immunity to the target antigen; a target antigen and CD1d co-expressing vector; a kit containing an expression vector and/or a CD1d ligand; and the like. | 09-16-2010 |
20100330057 | METHOD OF EVALUATING HUMAN DENTRITIC CELLS AND HUMAN CELL IMMUNOTHERAPEUTIC AGENT - The invention provides a method of evaluating the antigen presentation potential of human dendritic cells by administering α-galactosylceramide-pulsed human dendritic cells to a non-human mammal; collecting a sample containing NKT cells from the non-human mammal; and detecting the activation of NKT cells present in the sample. The invention further provides an agent for human NKT cell immunotherapy, which contains human dendritic cells that have been assessed by the aforementioned method as those possessing an antigen presentation potential for NKT cells. | 12-30-2010 |
20110020932 | IN VITRO DIFFERENTIATION/INDUCTION OF LYMPHOCYTE FROM STEM CELL HAVING GENOTYPE PROVIDED AFTER GENE RECONSTITUTION - The present invention provides a production method of a functional differentiated cell having a post-rearrangement genotype of a particular antigen receptor gene, which includes culturing a stem cell having the genotype in a medium to give the differentiated cell derived from the stem cell. As the stem cell having the genotype, a stem cell (e.g., ES cell) established by transplantation of the nucleus of a cell having the genotype is preferable. As the differentiated cell, NKT cell is preferable. | 01-27-2011 |
20130189302 | IMMUNOTHERAPEUTIC METHOD USING ARTIFICIAL ADJUVANT VECTOR CELLS THAT CO-EXPRESS CD1D AND TARGET ANTIGEN - Provided is immunotherapy of cancer or infection utilizing activation of dendritic cell (DC) by innate immunity, namely, a method of preparing an artificial adjuvant vector cell co-expressing a target antigen and CD1d and having an ability to activate immunity against the target antigen, comprising treating the target antigen and CD1d co-expressing cell with a CD1d ligand in a culture medium. | 07-25-2013 |
20140179004 | CELL FOR USE IN IMMUNOTHERAPY WHICH CONTAINS MODIFIED NUCLEIC ACID CONSTRUCT ENCODING WILMS TUMOR GENE PRODUCT OR FRAGMENT THEREOF, METHOD FOR PRODUCING SAID CELL, AND SAID NUCLEIC ACID CONSTRUCT - A cell of the present invention contains a nucleic acid construct encoding a WT1 gene product or a fragment of the WT1 gene product. The nucleic acid construct contains (i) a region encoding a desired fragment of the WT1 gene product and (ii) only AUG as a functional start codon. The present invention can provide a cell into which the nucleic acid construct is introduced so that an expression level of a WT1 gene product or a fragment of the WT1 gene product is remarkably enhanced. | 06-26-2014 |
Patent application number | Description | Published |
20130058608 | OPTICAL WAVEGUIDE AND ARRAYED WAVEGUIDE GRATING - A technique that does not increase the circuit size, does not make the circuit design and manufacturing difficult, and can reduce insertion loss when light enters from a slab waveguide toward an arrayed waveguide or when the light enters from the arrayed waveguide toward the slab waveguide. An optical waveguide provided with a slab waveguide in which a grating is formed therein at a distance from an end, and an arrayed waveguide whose end is connected to an end of the slab waveguide at a position where a constructive interference portion of a self-image of the grating is formed. An arrayed waveguide grating provided with a first input/output waveguide, the above-mentioned optical waveguide where an end of the slab waveguide on the opposite side of the arrayed waveguide is connected to an end of the first input/output waveguide, a second slab waveguide connected to an end of the arrayed waveguide on the opposite side of the slab waveguide, and a second input/output waveguide connected to an end of the second slab waveguide on the opposite side of the arrayed waveguide. | 03-07-2013 |
20130209036 | OPTICAL WAVEGUIDE AND ARRAYED WAVEGUIDE GRATING - An optical waveguide provided with a slab waveguide, which has a plurality of phase gratings arranged at a distance from each other in a direction substantially parallel to a light propagation direction and diffracting propagated light and a plurality of interference regions arranged alternately to the plurality of phase gratings in the direction substantially parallel to the light propagation direction and interfering the light diffracted by the plurality of phase gratings, and an arrayed waveguide whose end is connected to an end of the slab waveguide at a position of a constructive interference portion of a self-image formed by the plurality of phase gratings as an integrated phase grating. | 08-15-2013 |
20130279854 | OPTICAL WAVEGUIDE AND ARRAYED WAVEGUIDE GRATING - This optical waveguide is provided with a slab waveguide in which a grating is formed, an arrayed waveguide connected to a position where a constructive interference portion of a self-image of the grating is formed, and a refractive index change region which is formed between the slab waveguide and the arrayed waveguide, in which an average value of a refractive index in a refractive index distribution in a direction substantially vertical to a light propagation direction is averagely increased from the slab waveguide toward the arrayed waveguide, and in which an average value of the refractive index in a refractive index distribution in a direction substantially parallel to the light propagation direction is increased at a central axis of the arrayed waveguide. | 10-24-2013 |
Patent application number | Description | Published |
20120329369 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - According to one embodiment, a substrate processing method will be disclosed. The method includes attaching a substrate to be processed onto a supporting substrate via an adhesive layer, removing an outer peripheral edge portion of the substrate to be processed together with the adhesive sticking to the outer peripheral edge portion, and grinding a surface of a side opposite to the supporting substrate of the substrate to be processed whose outer peripheral edge portion is removed. | 12-27-2012 |
20130001766 | PROCESSING METHOD AND PROCESSING DEVICE OF SEMICONDUCTOR WAFER, AND SEMICONDUCTOR WAFER - According to one embodiment, a substrate processing method is disclosed. The above method includes: grinding an outer edge portion on a back surface of a semiconductor wafer with a semiconductor element formed on its front surface with a first grindstone or blade to thereby form an annular groove; grinding a projecting portion on an inner side of the groove with a second grindstone to thereby form a recessed portion integrally with the groove on the back surface of the semiconductor wafer; and grinding a bottom surface of the recessed portion including a ground surface made by the second grindstone with a third grindstone. | 01-03-2013 |
20130248099 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SUBSTRATE SEPARATING APPARATUS - According to one embodiment, there is disclosed a method of manufacturing a semiconductor device forming a release layer on a region excluding a peripheral edge portion of a surface of a first substrate, bonding a second substrate to at least a region including the release layer of the surface of the first substrate via an adhesive layer, removing physically a peripheral edge portion of the second substrate in a manner that at least a surface of the adhesive layer right under the peripheral edge portion of the second substrate is exposed, the adhesive layer is caused to remain between the peripheral edge portion of the first substrate and the second substrate, and adhesion between the first and second substrates is maintained, and then dissolving the adhesive layer. | 09-26-2013 |
Patent application number | Description | Published |
20090058273 | ORGANIC LIGHT-EMITTING APPARATUS - Provided is an organic light-emitting apparatus which can allow each of a plurality of organic light-emitting elements of different emission colors to emit light under optimum conditions. The organic light-emitting apparatus includes: a substrate; a plurality of organic light-emitting elements of different emission colors disposed on the substrate and each having formed sequentially on the substrate, a first electrode formed independently for each of the plurality of organic light-emitting elements, an organic functional layer, and a light-transmissive second electrode continuously formed extending over the plurality of organic light-emitting elements; a conductive layer formed between the substrate and the first electrode and electrically connected to the second electrode; and an insulating layer formed between the conductive layer and the first electrode, in which the insulating layer is different in at least one of thickness and material for each of the different emission colors. | 03-05-2009 |
20120006993 | SOLID-STATE IMAGING APPARATUS AND IMAGING SYSTEM - An imaging apparatus has an imaging area formed by arranging a plurality of imaging blocks each including a pixel array, a plurality of vertical signal lines, a horizontal output line commonly provided for the plurality of vertical signal lines to read out signals read out to the plurality of vertical signal lines, a first scanning circuit, and a second scanning circuit, wherein signals of the pixels of a selected row in the pixel array are read out to the plurality of vertical signal lines in accordance with a driving pulse from the first scanning circuit, the signals read out to the plurality of vertical signal lines are sequentially read out to the horizontal output line in accordance with a driving pulse from the second scanning circuit, and a length in a row direction of the pixel array is smaller than a length in a column direction of the pixel array. | 01-12-2012 |
20120007197 | SOLID-STATE IMAGING APPARATUS AND IMAGING SYSTEM - A solid-state imaging apparatus comprising a plurality of pixels each including a photoelectric conversion element, and a light shielding layer which covers the photoelectric conversion element is provided. The light shielding layer comprises a first light shielding portion which covers at least part of a region between the photoelectric conversion elements that are adjacent to each other, and a second light shielding portion for partially shielding light incident on the photoelectric conversion element of each of the plurality of pixels. An aperture is provided for the light shielding layer, the remaining component of the incident light passing through the aperture. A shape of the aperture includes a cruciform portion including a portion extending in a first direction and a portion extending in a second direction that intersects the first direction. | 01-12-2012 |
20120007203 | SOLID-STATE IMAGING APPARATUS AND IMAGING SYSTEM - A solid-state imaging apparatus including pixels each including a photoelectric conversion element, and a light shielding layer covering the photoelectric conversion element is provided. For each of the photoelectric conversion elements, the light shielding layer includes a light shielding portion which shields a portion of incident light to the photoelectric conversion element, and an aperture which passes another portion of the incident light. The pixels include first and second pixels which have different areas on a planar view of the photoelectric conversion element. The area of the photoelectric conversion element in the first pixel is larger than the area of the photoelectric conversion element in the second pixel on the planar view. An area of the light shielding portion included in the first pixel is larger than an area of the light shielding portion included in the second pixel. | 01-12-2012 |
20120008030 | SOLID-STATE IMAGING APPARATUS AND IMAGING SYSTEM - A solid-state imaging apparatus including a plurality of pixels each having a photoelectric conversion element, and an amplifier circuit which amplifies and outputs signals of the plurality of pixels is provided. The plurality of pixels include a first pixel having a first photoelectric conversion element with a first sensitivity and a second pixel having a second photoelectric conversion element with a second sensitivity higher than the first sensitivity. The amplifier circuit amplifies a signal output from the first pixel by a first gain and a signal output from the second pixel by a second gain smaller than the first gain. | 01-12-2012 |
20120008031 | SOLID-STATE IMAGING APPARATUS AND IMAGING SYSTEM - A solid-state imaging apparatus has a pixel array in which a plurality of pixels are arranged to form a plurality of rows and a plurality of columns, and a plurality of column signal lines are arranged, wherein each of the plurality of pixels includes a photoelectric converter including a first well formed in a semiconductor substrate and having a first conductivity type, and an impurity region arranged in the first well and having a second conductivity type different from the first conductivity type, and an in-pixel readout circuit which outputs, to the column signal line, a signal corresponding to charges generated in the photoelectric converter, the in-pixel readout circuit including a circuit element arranged in a second well having the first conductivity type, and wherein the first well and the second well are isolated by a semiconductor region having the second conductivity type. | 01-12-2012 |
20120008177 | SOLID-STATE IMAGING APPARATUS AND IMAGING SYSTEM - A solid-state imaging apparatus includes a pixel array in which a plurality of unit cells are arranged to form a plurality of rows and a plurality of columns, wherein each of the plurality of unit cells includes a pixel, and the pixel comprising a photoelectric conversion element and an in-pixel readout circuit which outputs a signal corresponding to charges generated in the photoelectric conversion element, power is supplied to the plurality of unit cells via a power supply line and a ground line, and at least one of the plurality of unit cells includes at least a part of a capacitive element having a first electrode connected to the power supply line and a second electrode connected to the ground line. | 01-12-2012 |
20120312964 | IMAGE PICKUP APPARATUS - An image pickup apparatus includes a plurality of pixels each including a read-out node to which an electric charge generated in a photoelectric conversion unit is transferred, an output unit configured to convert the electric charge transferred to the read-out node into a voltage and output the resultant voltage to a signal line, and a switch including a first node electrically connected to the read-out node. Each switch includes a second node different from the first node, and a particular number of second nodes are electrically connected to a common bypass wiring. | 12-13-2012 |
20130181117 | IMAGE PICKUP APPARATUS AND METHOD FOR DRIVING THE SAME - An image pickup apparatus of the present invention includes a clipping circuit that clips the voltage of an input node of an amplifying unit in a pixel. The clipping circuit can operate at least in a time period in which a charge is transferred from a photoelectric conversion unit to the input node of the amplifying unit, and can switch among multiple clipping voltages. | 07-18-2013 |
20130299678 | SOLID-STATE IMAGING APPARATUS AND IMAGING SYSTEM - An imaging apparatus has an imaging area formed by arranging a plurality of imaging blocks each including a pixel array, a plurality of vertical signal lines, a horizontal output line commonly provided for the plurality of vertical signal lines to read out signals read out to the plurality of vertical signal lines, a first scanning circuit, and a second scanning circuit, wherein signals of the pixels of a selected row in the pixel array are read out to the plurality of vertical signal lines in accordance with a driving pulse from the first scanning circuit, the signals read out to the plurality of vertical signal lines are sequentially read out to the horizontal output line in accordance with a driving pulse from the second scanning circuit, and a length in a row direction of the pixel array is smaller than a length in a column direction of the pixel array. | 11-14-2013 |
20150070554 | SOLID-STATE IMAGING APPARATUS, DRIVING METHOD FOR THE SAME, AND IMAGING SYSTEM - A solid-state imaging apparatus includes: a photoelectric conversion unit configured to convert light into an electric charge; a floating diffusion region configured to convert the electric charge into a voltage; a transfer transistor configured to transfer the electric charge from the photoelectric conversion unit to the floating diffusion region; and a transfer transistor driving circuit configured to control a gate potential of the transfer transistor, wherein the transfer transistor driving circuit controls the gate potential so as to be changed in at least two changing rates during a period of transition from the ON state to the OFF state of the transfer transistor, and the second changing rate out of the two changing rates is higher than the first changing rate. | 03-12-2015 |
20150189210 | SOLID-STATE IMAGING APPARATUS AND DRIVING METHOD THEREFOR - A solid-state imaging apparatus of this invention includes a plurality of pixels arranged in a matrix and configured to generate signals by photoelectric conversion, a plurality of signal lines each provided on each column of the pixels, and a plurality of column circuits each provided for each of the signal lines. It is possible to select one of a first readout operation of simultaneously processing the signals of the pixels on a plurality of rows by the plurality of column circuits and a second readout operation of simultaneously processing the signal of the same pixel by different gains by the plurality of column circuits. | 07-02-2015 |
Patent application number | Description | Published |
20110141811 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device of the invention comprises a memory cell array which includes a first region that has a plurality of memory cells each capable of storing n-bit data (n is a natural number) and a second region that has a plurality of memory cells each capable of storing k-bit data (k>n: k is a natural number), a data storage circuit which includes a plurality of data caches, and a control circuit which controls the memory cell array and the data storage circuit in such a manner that the k-bit data read from the k/n number of memory cells in the first region are stored into the data storage circuit and the k-bit data are stored into the memory cells in the second region. | 06-16-2011 |
20120265949 | SEMICONDUCTOR MEMORY SYSTEM - According to one embodiment, a semiconductor memory system includes semiconductor memories, and a memory controller configured to control the semiconductor memories. Each of the semiconductor memories is configured to execute an internal sequence including operations and have a wait period after an end of each of the operations, to notify, during the wait period, a status signal, which notifies in advance a start of a next operation, to the memory controller, and to start the next operation upon receiving a restart instruction of the internal sequence from the memory controller. | 10-18-2012 |
20130145083 | Semiconductor Memory Device - According to one embodiment, a semiconductor memory device includes a memory which comprises an area accessible from outside and a confidential information area storing confidential information and a set flag. A controller reads the flag from the memory when instructed to erase data in the confidential information area, determines whether the flag is set, erases data in the confidential information area when the flag is clear, and abandons process requested by the data erase instruction when the flag is set. An authenticator uses data in the confidential information area to execute operation for authentication. | 06-06-2013 |
Patent application number | Description | Published |
20100102541 | AUTOMOTIVE AIRBAG APPARATUS - An automotive airbag apparatus is able to reduce the shock caused by early deployment of airbag against a passenger not in a position for safe airbag restraint, and further able to deploy quickly and effectively when a passenger is in a position for safe restraint. The airbag apparatus includes an airbag housing in which a folded airbag resides until deployed by the gas from an inflator, an airbag door that opens on a hinge from the pressure applied by the deploying airbag, and a restrictor member extending over the folded airbag beneath the airbag door with a direction from front to rear of the vehicle. The restrictor member has a fixed end at forward part thereof attached to the airbag housing, and a releasable fixed or free end at rearward part thereof, the free end coming into frictional contact with the airbag door in the vicinity of the hinge as the airbag door is pushed out by the early phase of the airbag deployment. | 04-29-2010 |
20150090830 | WINDING APPARATUS AND WINDING METHOD - According to one embodiment, winding apparatus includes a bobbin, a core, a pressing section, a moving unit, a first rotating unit, a second rotating unit and a control unit. The moving unit is configured to move the pressing section relatively to the core along each of first to third axes perpendicular to each other. The first rotating unit is configured to rotate the pressing section relatively to the core around fourth and fifth axes perpendicular to each other, and set on the core. The second rotating unit is configured to rotate the pressing section relatively to the core around a sixth axis which becomes parallel to, when the core is in an initial position at which the fourth and fifth axes become parallel to any two of the first to third axes, a remaining one of the first to third axes. | 04-02-2015 |
Patent application number | Description | Published |
20080253173 | MAGNETIC RANDOM ACCESS MEMORY - A magnetic random access memory according to an example of the invention comprises a first reference bit line shared by first reference cells, a second reference bit line shared by second reference cells, a first driver-sinker to feed a first writing current, a second driver-sinker to feed a second writing current, and a control circuit which checks data stored in the first and second reference cells line by line, and executes writing simultaneously to all of the first and second reference cells by a uniaxial writing when the data is broken. | 10-16-2008 |
20090003103 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY TESTER - A semiconductor device, a semiconductor memory tester, and a multi-chip package are provided. The semiconductor device includes a plurality of nonvolatile semiconductor memories; a boosting circuit which generates a boosted voltage for operating the plurality of nonvolatile semiconductor memories; and a boosting circuit controller which controls the operation of the boosting circuit to generate the boosted voltage on the basis of an operation sequence of the plurality of nonvolatile semiconductor memories. | 01-01-2009 |
20090067212 | MAGNETIC RANDOM ACCESS MEMORY AND DATA READ METHOD OF THE SAME - A magnetic random access memory includes a memory element having a first fixed layer, a first recording layer, and a first nonmagnetic layer, a first reference element having a second fixed layer, a second recording layer, and a second nonmagnetic layer, antiparallel data being written in the first reference element, a second reference element making a pair with the first reference element, and having a third fixed layer, a third recording layer, and a third nonmagnetic layer, parallel data being written in the second reference element, and a current source which, when a read operation is performed, supplies a current from the second fixed layer to the second recording layer in the first reference element, and supplies the current from the third recording layer to the third fixed layer in the second reference element. | 03-12-2009 |
20090122611 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME - This disclosure concerns a memory including cell blocks, wherein in a first write sequence for writing data to a first cell block, drivers write the data only to memory cells arranged in a form of a checkered flag among the memory cells included in the first cell block, in a second write sequence for writing the data from the first cell block to a second cell block, the drivers write the data to all memory cells connected to a word line selected in the second cell block, and when the data is read from the first cell block or at a time of data verification when data is written to the first cell block, the word line drivers simultaneously apply a read voltage to two adjacent word lines, and the sense amplifiers detects the data in the memory cells connected to the two word lines. | 05-14-2009 |
20090135638 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF IDENTIFYING A PLURALITY OF MEMORY CHIPS STACKED IN THE SAME PACKAGE - A semiconductor memory device is configured to vertically stack a plurality of memory chips using a resistance-change memory element as a memory cell in one package. The memory chips each have first and second memory position detection pads connected via chip top and bottom electrodes facing each other. Of the vertically stacked memory chips, the lowermost memory chip is provided with the connected chip bottom electrodes of the first and second memory position detection pads. The memory chips each control the variable resistance element, and in a state that the first memory position detection pad has a higher resistance than the second memory position detection pad, compare a voltage applied to the first memory position detection pad with the chip position detection signal using the comparator when a voltage is applied between the first and second memory position detection pads provided on the uppermost layer memory chip. | 05-28-2009 |
20090238003 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage. | 09-24-2009 |
20110074494 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY TESTER - A semiconductor device, a semiconductor memory tester, and a multi-chip package are provided. The semiconductor device includes a plurality of nonvolatile semiconductor memories; a boosting circuit which generates a boosted voltage for operating the plurality of nonvolatile semiconductor memories; and a boosting circuit controller which controls the operation of the boosting circuit to generate the boosted voltage on the basis of an operation sequence of the plurality of nonvolatile semiconductor memories. | 03-31-2011 |
20110242892 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage. | 10-06-2011 |
20110267864 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a first memory chip, a second memory chip, and a control chip. The first chip includes a first inductor configured to transmit/receive a signal, and a memory cell. The second chip is disposed on the first chip and includes a second inductor configured to transmit/receive a signal, and a memory cell. The control chip includes a control circuit configured to control the first and second chips, and a third inductor configured to transmit/receive a signal to/from the first and second inductors. The outer peripheries of the first and second inductors are included in a closed space produced by extending the outer periphery of the third inductor in a direction perpendicular to a plane that includes the third inductor. The inductance of the third inductor is greater than at least one of the inductances of the first and second inductors. | 11-03-2011 |
20110305086 | SEMICONDUCTOR MEMORY DEVICE - A memory includes stacking chips. The chip includes a pad commonly connected to the chips and receiving an enable signal that enables access to each chip. The chip includes a chip address memory that can store a chip address. The chip includes a determining part comparing a select address to the chip address for determining whether they match each other. The chip includes a control-signal setting part setting the control signal inputted to the chip itself to be valid or invalid depending on a determination made by the determining part. The chip includes a chip-address setting part determining whether the chip address is stored in the chip address memory depending on number of fail bits. The device includes a memory controller allocating respectively different ones of the chip addresses to the chips based on the number of fail bits. | 12-15-2011 |
20120069530 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a stacked chip includes semiconductor chips which are stacked, the semiconductor chips comprises semiconductor substrates and through electrodes formed in the semiconductor substrates, respectively, the through electrodes being electrically connected, and deactivating circuits provided in the semiconductor chips, respectively, and configured to deactivate a failed semiconductor chip. | 03-22-2012 |
20130250693 | MEMORY SYSTEM - According to one embodiment, a memory system includes a first semiconductor memory and a controller. The first semiconductor memory receives a first clock, and outputs, in accordance with the first clock, a second clock and a data signal in synchronization with the second clock. The controller includes a detection circuit which detects a shift of a duty ratio of the second clock which is output from the first semiconductor memory. The controller also includes an adjustment circuit which adjusts a duty ratio of the first clock based on the shift detected by the detection circuit. | 09-26-2013 |