Patent application number | Description | Published |
20080237831 | MULTI-CHIP SEMICONDUCTOR PACKAGE STRUCTURE - A multi-chip semiconductor package structure is disclosed according to the present invention, the package structure includes: a carrier board having a first surface, a second surface, and at least an opening penetrating the first and second surfaces, the first and second surfaces each having electrically connecting pads; a semiconductor component received in the opening, the semiconductor component has a first active surface and a second active surface, and each of the first and second active surfaces has a plurality of electrode pads; a plurality of first conductive elements electrically connected to the electrically connecting pads of the first and second surfaces of the carrier board with the electrode pads of the first and second active surfaces of the semiconductor component; and a molding material formed on a portion of the first surface of the carrier board, the first active surface of the semiconductor component, a portion of the second surface of the carrier board, and the second active surface of the semiconductor component, and adapted to cover the first conductive elements; thereby forming a module structure for electrical connection with other modules or stacked devices, and further enhancing electrical functions. | 10-02-2008 |
20080237832 | MULTI-CHIP SEMICONDUCTOR PACKAGE STRUCTURE - A multi-chip semiconductor package structure is disclosed, including a carrier board having a first and an opposing second surfaces and formed with at least an opening penetrating the first and second surfaces, wherein a plurality of electrically connecting pads are formed on the first and second surfaces of the carrier board, respectively; a semiconductor component disposed in the opening, the semiconductor component having a first and a second active surfaces each with a plurality of electrode pads being formed thereon; a third semiconductor chip having an active surface and an inactive surface, the active surface having a plurality of electrode pads formed thereon for electrically connecting with the electrically connecting pads on the first surface of the carrier board and the electrode pads on the first active surface of the semiconductor component; and a fourth semiconductor chip having an active surface and an inactive surface, the active surface having a plurality of electrode pads formed thereon for electrically connecting with the electrically connecting pads on the second surface of the carrier board and the electrode pads on the second active surface of the semiconductor component, thereby providing a modularized structure for electrically connecting with other modules or stack devices and enhancing electrical functionality. | 10-02-2008 |
20080237833 | MULTI-CHIP SEMICONDUCTOR PACKAGE STRUCTURE - A multi-chip semiconductor package structure is disclosed according to the present invention. The package structure includes: a carrier board having a first surface, a second surface, and at least one opening penetrating the first and second surfaces, the first and second surfaces each being formed with a plurality of electrically connecting pads thereon; a semiconductor component received in the opening and having first and second active surfaces, the first and second active surfaces each being formed with a plurality of electrode pads thereon; a plurality of first conductive elements electrically connected to the electrically connecting pads on the second surface of the carrier board and the electrode pads on the second active surface of the semiconductor component; a semiconductor chip having an active surface and an inactive surface, the active surface having a plurality of electrode pads electrically connected to the electrically connecting pads on the first surface of the carrier board and the electrode pads on the first active surface of the semiconductor component; and a molding material formed on a portion of the second surface of the carrier board and the second active surface of the semiconductor component to cover the first conductive elements. The present invention provides a modularized structure capable of electrically connecting to other modules or stacked devices as well as enhancing electrical performance. | 10-02-2008 |
20080264677 | Circuit board structure having embedded capacitor and fabrication method thereof - The present invention provides a circuit board structure having an embedded capacitor and a method for fabricating the same. The circuit board structure includes a core layer board with at least one surface having non-penetrating first and second grooves, a circuit layer and a first electrode plate formed in the first and second grooves of the core layer board respectively and being flush with the core layer board; a high dielectric material layer formed on the core layer board, the circuit layer and the first electrode plate; a second electrode plate formed on the high dielectric material layer and corresponding to the first electrode plate, thereby forming a capacitor by the first and second electrode plates and the high dielectric material layer. The high dielectric material layer is formed on a plane surface so as to eliminate poor filling and improve reliability. | 10-30-2008 |
20080290528 | SEMICONDUCTOR PACKAGE SUBSTRATE HAVING ELECTRICAL CONNECTING PADS - A semiconductor package substrate having electrical connecting pads includes: a substrate body having a plurality of electrical connecting pads formed on surface thereof, and a plurality of protruding lumps or concave areas of any geometric shape respectively formed on surfaces of the electrical connecting pads for increasing contact surfaces of the electrical connecting pads, thereby preventing detaching of conductive elements from surfaces of the electrical connecting pads caused by poor bonding force. | 11-27-2008 |
20090000813 | PACKAGING SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOF - A packaging substrate structure includes a dielectric layer with a plurality of dielectric pillars disposed on a portion of a large-dimension opening area of the dielectric layer; and a first circuit layer with a plurality of first circuits disposed on a portion of the dielectric layer, and a conductive block disposed in the large-dimension opening area of the dielectric layer having the dielectric pillars. The dielectric pillars reduce the difference of the electrical current density distribution between the large-dimension opening area and small-dimension opening areas during electroplating, thereby overcoming the conventional drawback of insufficient thickness or a hollow center of the conductive block that results in an uneven thickness of the circuit layer. The invention further provides a method of manufacturing the packaging substrate structure. | 01-01-2009 |
20090020322 | PACKAGING SUBSTRATE WITH CONDUCTIVE STRUCTURE - A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump covering the surfaces of the metal post. Therefore, a highly reliable conductive structure is provided, by using the stress buffer metal layer to release thermal stresses, and using the metal post and the solder bump to increase the height of the conductive structure. | 01-22-2009 |
20090032294 | CIRCUIT BOARD - Provided is a circuit board including: a circuit board body with at least one surface having a plurality of electrically connecting pads; an insulating protection layer formed on the circuit board body and formed with an opening corresponding in position to one of the electrically connecting pads, being larger than the electrically connecting pad, and not being in contact with the periphery of the electrically connecting pad; and a soldering material formed on, and confined to, the electrically connecting pad; thus allowing an electrically conductive element limited in the opening formed in the insulating protection layer to be fabricated from the soldering material by a reflow process with a view to forming a fine-pitch electrically connecting structure. | 02-05-2009 |
20090041981 | PACKAGING SUBSTRATE HAVING ELECTRICAL CONNECTION STRUCTURE AND METHOD FOR FABRICATING THE SAME - A packaging substrate having an electrical connection structure and a method for fabricating the same are provided. The packaging substrate have a substrate body with a plurality of conductive pads on a surface thereof; a solder mask layer disposed on the substrate body with a plurality of openings corresponding to the conductive pads, the size of each of the openings being larger than each of the conductive pads; and electroplated solder bumps for covering the conductive pads to provide better bond strength and reliability. | 02-12-2009 |
20090065245 | CIRCUIT BOARD STRUCTURE AND FABRICATION METHOD THEREOF - A circuit board structure and a fabrication method thereof are disclosed. The circuit board structure includes a carrying board having a first and an opposite second surface and having at least one through cavity formed therein; a semiconductor chip disposed in the through cavity of the carrying board; an adhesive material filling the gap between the through cavity of the carrying board and the semiconductor chip to fix the semiconductor chip in the through cavity; and a reinforcing layer disposed on the second surface of the carrying board and the inactive surface of the semiconductor chip, thereby increasing the strength of the carrying board as well as the reliability of the circuit board. | 03-12-2009 |
20090081861 | MANUFACTURING METHOD OF SOLDER BALL DISPOSING SURFACE STRUCTURE OF PACKAGE SUBSTRATE - A manufacturing method of a solder ball disposing surface structure on a core board including: providing a core board with a first metal layer and an opposing metal bump-equipped second metal layer; forming resists on the first and second metal layers respectively; forming third, fourth and fifth openings in the resists; removing the first and second metal layers in the third and fourth openings to form first and second circuit layers and metal pads respectively; removing the metal bumps in the fifth openings to form metal flanges; removing the resists; forming first and second insulative protection layers on the first and second circuit layers and metal pads respectively; forming first and second openings in the first and second insulative protection layers to expose the first circuit layer as electrical connecting pads and expose the metal flanges respectively. Accordingly, increased contact surface area for mounting conductive elements prevents detachment thereof. | 03-26-2009 |
20090091903 | Stack structure of circuit boards embedded with semiconductor chips - A stack structure of circuit boards embedded with semiconductor chips is proposed. At least two circuit boards are provided. Each of the circuit boards includes circuit layers formed on surfaces thereof and at least one opening embedded with a semiconductor chip, wherein, the circuit layers have a plurality of conductive structures and electrically conductive pads, and the semiconductor chip has a plurality of electrode pads, and the conductive structures of the circuit layers are electrically conductive to the electrode pads of the semiconductor chip. At least one adhesive layer is formed between the two circuit boards and disposed with a conductive material corresponding in position to the electrically conductive pads of the circuit boards. Thus, a conductive path can be formed by the conductive material between the electrically conductive pads of the circuit boards, thereby establishing electrical connection between the two circuit boards. | 04-09-2009 |
20090096099 | PACKAGE SUBSTRATE AND METHOD FOR FABRICATING THE SAME - A package substrate and a method for fabricating the same are provided according to the present invention. The package substrate includes: a substrate body with a die attaching side and a ball implanting side lying opposite each other, having a plurality of wire bonding pads and a plurality of solder ball pads respectively, and having a first insulating passivation layer and a second insulating passivation layer respectively, wherein a plurality of first apertures and a plurality of second apertures are formed in the first insulating passivation layer and the second insulation passivation layer respectively to corresponding expose the wire bonding pads and the solder ball pads; a chemical plating metal layer formed on the wire bonding pads and solder ball pads respectively; and a wire bonding metal layer formed on a surface of the chemical plating metal layer of the wire bonding metal layer. | 04-16-2009 |
20090102050 | SOLDER BALL DISPOSING SURFACE STRUCTURE OF PACKAGE SUBSTRATE - A solder ball disposing surface structure of a package substrate is disclosed, wherein a package substrate has a chip disposing surface with a first circuit layer, an opposed solder ball disposing surface with a second circuit layer, and a first insulative protection layer formed on the chip disposing surface and the first circuit layer. The solder ball disposing surface structure includes: metal pads integral to the second circuit layer; metal flanges formed around the metal pads; and a second insulative protection layer formed on the solder ball disposing surface, the second insulative protection layer having second openings each with a size smaller than an outer diameter of each of the metal flanges so as to expose a part of surfaces of the metal flanges, thereby increasing contact area of the surface for mounting conductive elements and preventing detachment of the conductive elements from the surface due to poor bonding force. | 04-23-2009 |
20090129040 | Circuit board having power source - A circuit board having a power source is provided, including: a carrier board having a first dielectric layer disposed on at least a surface thereof and a first circuit layer disposed on the first dielectric layer, wherein the first circuit layer has at least an electrode pad; a first electrode plate disposed on the electrode pad; an insulating frame member disposed on the first electrode plate, with a portion of the first electrode plate being exposed from the insulating frame member, wherein electrolyte is received in the insulating frame member and in contact with the first electrode plate; and a porous second electrode plate disposed on the insulating frame member and the electrolyte, the second electrode plate being in contact with the electrolyte, so as to provide the power source for the circuit board. | 05-21-2009 |
20090166841 | PACKAGE SUBSTRATE EMBEDDED WITH SEMICONDUCTOR COMPONENT - A package substrate embedded with a semiconductor component includes a substrate, a semiconductor chip, a first dielectric layer, a first circuit layer and first conductive vias. The substrate is formed with an opening for allowing the semiconductor chip to be secured therein. The semiconductor chip has an active surface and an inactive surface, wherein a plurality of electrode pads are formed on the active surface thereof and a passivation layer disposed thereon. The first dielectric layer is disposed both on the substrate and the passivation layer, wherein vias are formed at locations corresponding to those of the electrode pads and penetrating the dielectric layer and the passivation layer to expose the electrode pads therefrom. The first circuit layer is disposed on the first dielectric layer and electrically connected to the first conductive vias. The first conductive vias are disposed in the openings of the dielectric and passivation layers and the first circuit layer is electrically connected to the electrode pads, thereby allowing the first conductive vias to be electrically connected to the electrode pads of the chip. | 07-02-2009 |
20090168380 | PACKAGE SUBSTRATE EMBEDDED WITH SEMICONDUCTOR COMPONENT - A package substrate embedded with a semiconductor component is provided. A semiconductor chip is received in a cavity of a substrate body, and has electrode pads on an active surface thereof. A passivation layer is disposed on the active surface and has openings for exposing the electrode pads. An electroless plating metal layer, a first sputtering metal layer and a second sputtering metal layer are sequentially formed on the electrode pads, the openings of the passivation layer and the passivation layer surface around the openings. Contact pads are formed on the second sputtering metal layer. A first dielectric layer is disposed on the substrate body and the passivation layer. A first circuit layer is formed on the first dielectric layer. First conductive vias are formed in the first dielectric layer and electrically connected to the contact pads. The first circuit layer is electrically connected to the first conductive vias. | 07-02-2009 |
20090200658 | CIRCUIT BOARD STRUCTURE EMBEDDED WITH SEMICONDUCTOR CHIPS - A circuit board structure embedded with semiconductor chips is proposed. A semiconductor chip is received in a cavity of a supporting board. A dielectric layer and a circuit layer are formed on the supporting board and the semiconductor chip. A plurality of hollow conductive vias are formed in the dielectric layer for electrically connecting the circuit layer to the semiconductor chip. By providing the hollow conductive vias of present invention, the separating results of different coefficients of expansion and thermal stress are prevented, and thus electrical function of products is ensured. | 08-13-2009 |
20090294962 | PACKAGING SUBSTRATE AND METHOD FOR FABRICATING THE SAME - A packaging substrate and a method for fabricating the same are proposed, including: providing a substrate body having a first surface and an opposing second surface, wherein the first surface has a plurality of flip-chip solder pads and wire bonding pads and the second surface has a plurality of solder ball pads; forming a first and a second solder mask layers on the first and second surfaces respectively and forming openings in the first and second solder mask layers to expose the flip-chip solder pads, the wire bonding pads and the solder ball pads; forming first bumps on the flip-chip solder pads; and forming an electroless Ni/Pd/Au layer on the first bumps and the wire bonding pads by electroless plating, wherein the electroless Ni/Pd/Au layer has a thickness tolerance capable of meeting evenness requirements for fine pitch applications. | 12-03-2009 |
20090309179 | PACKAGE SUBSTRATE HAVING EMBEDDED PHOTOSENSITIVE SEMICONDUCTOR CHIP AND FABRICATION METHOD THEREOF - A packaging substrate with an embedded photosensitive semiconductor chip and a method for fabricating the same are provided. The method includes the steps of: disposing the semiconductor chip in an through cavity of a core board with the photosensitive portion of the semiconductor chip being exposed from the through cavity; forming a first circuit layer on the core board at a side opposite to the photosensitive portion so as to electrically connect the electrode pads of the semiconductor chip; and forming a light-permeable layer on the core board at the same side with the photosensitive portion via an adhesion layer so as to allow light to penetrate through the light-permeable layer and reach the photosensitive portion of the semiconductor chip. When fabricated by the method, the packaging substrate dispenses with conductive wires and a surrounding dam and thus is efficiently downsized. | 12-17-2009 |
20130183800 | CIRCUIT BOARD STRUCTURE AND FABRICATION THEREOF - A circuit board structure and a fabrication method thereof are disclosed. The circuit board structure includes a carrying board having a first and an opposite second surface and having at least one through cavity formed therein; a semiconductor chip disposed in the through cavity of the carrying board; an adhesive material filling the gap between the through cavity of the carrying board and the semiconductor chip to fix the semiconductor chip in the through cavity; and a reinforcing layer disposed on the second surface of the carrying board and the inactive surface of the semiconductor chip, thereby increasing the strength of the carrying board as well as the reliability of the circuit board. | 07-18-2013 |