Shih-Lin
Shih-Lin Chang, Taipei TW
Patent application number | Description | Published |
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20130334025 | HIGH-PERFORMANCE DIFFUSION MULTIPLE-EFFECT DISTILLATION SYSTEM - A high-performance diffusion multiple-effect distillation system, which comprising: a few distillers, a heating device and a water make-up device; said distiller is composed of several laminar distillation sheets, with one surface taken as a condensing surface, and the other surface attached with an evaporating sheet; a collecting ditch is set below the condensing surface; and the periphery of the distillation sheets is provided with a supporting structure; the heating device is provided with several heating surfaces; the heating surface and the condensing surface of corresponding distillation sheet have a good thermal contact, the water make-up device is provided with at least a water tank filled with water to be distilled and at least a water make-up body. | 12-19-2013 |
20140042009 | MULITI-EFFECT DISTILLATION DEVICE - Present invention is a practical, highly efficient, structurally simple, low production cost, easy to manufacturing, and inexpensive multi-effect distillation device composed of thin-laminated distiller which is tangled into spiral and becomes layers of centric circle; one side of surface of said distiller is condensing surface which is for condensation of vapor of water, condensed distilled water is drained from underneath of said condensing surface, another side of said distiller is attached with a piece of wick which is made of capillary materials, undistilled water enters from above of the wick, than be absorbed and distributed by said wick. Some of the water absorbed on said wick is evaporated into the vapor of water. There is a gap between condensing surface and wick of each adjacent layers. The top and bottom of said gap is sealed to prevent leaking of the vapor of water. | 02-13-2014 |
Shih-Lin Huang, Penghu TW
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20120182804 | ARCHITECTURE FOR A 3D MEMORY ARRAY - Techniques are described herein for compensating for threshold voltage variations among memory cells in an array by applying different bias conditions to selected bit lines. Techniques are also described herein for connecting global bit lines to a variety of levels of memory cells in a 3D array, to provide for minimizing capacitance differences among the global bit lines. | 07-19-2012 |
20130343130 | NAND FLASH BIASING OPERATION - A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a bias for performing an operation on a selected cell of the NAND array. The bias includes charging the bit line while the string select switches are closed, such as to not introduce noise into the strings caused by such bit line charging. The semiconductor body regions in memory cells that are on both sides of the memory cells in the NAND strings that are coupled to a selected word line are coupled to reference voltages such that they are pre-charged while the word lines of the strings in the array are transitioned to various voltages during the operation. | 12-26-2013 |
20140198576 | PROGRAMMING TECHNIQUE FOR REDUCING PROGRAM DISTURB IN STACKED MEMORY STRUCTURES - A programming bias technique is described for programming a stacked memory structure with a plurality of layers of memory cells. The technique includes the controller circuitry responsive to a program instruction to program data in target cells in a stack of cells at a particular multibit address. The circuitry is configured to use an assignment of cells in the stack of cells to a plurality of sets of cells, and to iteratively execute a set program operation selecting each of the plurality of sets in sequence. Each iteration includes applying inhibit voltages to all of the cells in others of the plurality of sets. Also, each set of layers includes subsets of one or two, and there are at least two layers from other sets separating each of the subsets in one set. | 07-17-2014 |
Shih-Lin Huang, Magong City TW
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20140254284 | WORD LINE DRIVER CIRCUIT FOR SELECTING AND DESELECTING WORD LINES - A memory circuit includes word lines coupled to a memory array, including a first set of one or more word lines deselected in an erase operation, and a second set of one or more word lines selected in the erase operation. Control circuitry couples the first set of one or more word lines deselected in the erase operation to a reference voltage, responsive to receiving an erase command for the erase operation. Some examples further include a first transistor that switchably couples a word line to a global word line, and a second transistor that switchably couples the word line to a ground voltage. The control circuitry is coupled to the first transistor and the second transistor, wherein the control circuitry has a plurality of modes including at least an erase operation. In a first mode, the first transistor couples the word line to the global word line, and the second transistor decouples the word line from the ground voltage. In a second mode, the first transistor decouples the word line from the global word line, and the second transistor couples the word line to the ground voltage. | 09-11-2014 |
Shih-Lin Lee, Taipei TW
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20080251109 | Lighting and Alerting Device for Walking Stick - A lighting and alerting device for a walking stick includes a walking stick body and a control device. The control device includes a manual power generating unit and a power supply unit; electric power generated by winding the manual power generating unit is transmitted to a power storing unit for storage, and is further transmitted to a lighting unit, a light alerting unit and a sound alerting unit; the power supply unit also supplies electric power to the lighting unit, the light alerting unit and the sound alerting unit. Normally, the lighting unit, the light alerting unit and the sound alerting unit receives a power signal from the power supply unit so as to let the user to use a control switch to enable operations of the lighting unit, the light alerting unit and the sound alerting unit, to allow the walking stick to provide lighting and alerting functions during nighttime. If the power supply unit is running out of power, the user can wind the manual power generating unit to generate temporary power to enable operations of the lighting unit, the light alerting unit and the sound alerting unit. | 10-16-2008 |
Shih-Lin Lee, San Jose, CA US
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20140169074 | MEMORY ELEMENTS WITH STACKED PULL-UP DEVICES - Integrated circuits with memory cells are provided. A memory cell may include first and second cross-coupled inverting circuits configured to store a single data bit. The first inverting circuit may have an output serving as a first data storage node for the memory cell, whereas the second inverting circuit may have an output serving as a second data storage node for the memory cell. Access transistors may be coupled between the first and second data storage nodes and corresponding data lines. Each of the first and second inverting circuit may have a pull-down transistor and at least two pull-up transistors stacked in series. The pull-down transistors may have body terminals that are reverse biased to help reduce leakage current through the first and second inverting circuits. The memory cell may be formed using a narrower two-gate configuration or a wider four-gate configuration. | 06-19-2014 |