Patent application number | Description | Published |
20090014704 | CURRENT CONSTRICTING PHASE CHANGE MEMORY ELEMENT STRUCTURE - A layer of nanopaiticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer. | 01-15-2009 |
20100193763 | CURRENT CONSTRICTING PHASE CHANGE MEMORY ELEMENT STRUCTURE - A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer. | 08-05-2010 |
20120016472 | Color Tactile Vision System - A tactile display writer unit includes a probe having a contact tip, and at least a first actuator and a second actuator coupled to the probe, whereby activation of the actuators results in a displacement of the probe tip in one or more of a z-direction and in a lateral direction having a vector in an x-y plane. Also, a display writer includes a plurality of such units supported in an x-y array. The writer units may have a third actuator coupled to the probe. Also, a tactile vision system includes such a display writer, an image processor, and an image sensor. The processor transforms RGB image information from the image sensor into hue-based information having two or more attributes; and the actuators in the tactile display writer are activated by the information attributes. Also, a method for producing a tactile color stimulus at a site on the skin of a subject includes providing a probe having a contact tip; displacing the tip at the contact site in a direction generally normal to the skin surface at the site to an extent that relates one attribute of a hue-based model of the color, and displacing the tip in at least one lateral direction generally in a plane parallel to the skin surface at the site to an extent that relates to at least one additional attribute of the color. | 01-19-2012 |
20120104542 | Semiconductor Structure With Contact Structure and Manufacturing Method of the Same - The invention relates to a semiconductor structure and a manufacturing method of the same. The semiconductor structure includes a semiconductor substrate, an isolation layer, a first metal layer, and a second metal layer. The semiconductor substrate includes an upper substrate surface and a semiconductor device below the upper substrate surface. The isolation layer has opposite a first side wall and a second side wall. The first metal layer is disposed on the upper substrate surface. The first metal layer and the second metal layer are disposed on the first side wall and the second side wall, respectively. A lower surface of the second metal layer is below the upper substrate surface. | 05-03-2012 |
20120168841 | Multiple Patterning Method - An integrated circuit memory comprises a set of lines each line having parallel X direction line portions in a first region and Y direction line portions in a second region. The second region is offset from the first region. The lengths of the X direction line portions are substantially longer than the lengths of the Y direction line portions. The X direction and Y direction line portions have respective first and second pitches with the second pitch being at least 3 times larger than the first pitch. Contact pickup areas are at the Y direction line portions. In some examples, the lines comprise word lines or bit lines. The memory can be created using multiple patterning methods to create lines of material and then the parallel X direction line portions and parallel Y direction line portions. | 07-05-2012 |
20120168955 | Integrated Circuit Pattern and Method - An integrated circuit pattern comprises a set of lines of material having X and Y direction portions. The X and Y direction portions have first and second pitches, the second pitch being larger, such as at least 3 times larger, than the first pitch. The X direction portions are parallel and the Y direction portions are parallel. The end regions of the Y direction portions comprise main line portions and offset portions. The offset portions comprise offset elements spaced apart from and electrically connected to the main line portions. The offset portions define contact areas for subsequent pattern transferring procedures. A multiple patterning method, for use during integrated circuit processing procedures, provides contact areas for subsequent pattern transferring procedures. | 07-05-2012 |
20120181580 | Semiconductor Structure and Manufacturing Method of the Same - A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a stacked structure, a dielectric element, a conductive line, and conductive islands. The stacked structure is formed on the substrate. The stacked structure includes conductive strips and insulating strips stacked alternately. The conductive strips are separated from each other by the insulating strips. The dielectric element is formed on the stacked structure. The conductive line is formed on the dielectric element. The conductive line is extended in a direction perpendicular to a direction which the stacked structure is extended in. The conductive islands are formed on the dielectric element. The conductive islands on the opposite sidewalls of the single stacked structure are separated from each other. | 07-19-2012 |
20120181699 | Semiconductor Structure and Manufacturing Method of the Same - A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first stacked structure, a second stacked structure, a dielectric element, and a conductive line. The first stacked structure and the second stacked structure are disposed on the substrate. Each of the first stacked structure and the second stacked structure includes conductive strips and insulating strips stacked alternately. The conductive strips are separated from each other by the insulating strips. The dielectric element is disposed on the first stacked structure and the second stacked structure and includes a second dielectric portion. The first stacked structure and the second stacked structure are separated from each other by only the second dielectric portion. The conductive line is disposed on the stack sidewalls of the first stacked structure and the second stacked structure far from the second dielectric portion. | 07-19-2012 |
20120181701 | Multilayer Connection Structure and Making Method - A method provides electrical connections to a stack of contact levels of an interconnect region for a 3-D stacked IC device. Each contact level comprises conductive and insulation layers. A portion of any upper layer is removed to expose a first contact level and create contact openings for each contact level. A set of N masks is used to etch the contact openings up to and including 2 | 07-19-2012 |
20120182808 | Memory Device, Manufacturing Method and Operating Method of the Same - A memory device, a manufacturing method and an operating method of the same are provided. The memory device includes a substrate, stacked structures, a channel element, a dielectric element, a source element, and a bit line. The stacked structures are disposed on the substrate. Each of the stacked structures includes a string selection line, a word line, a ground selection line and an insulating line. The string selection line, the word line and the ground selection line are separated from each other by the insulating line. The channel element is disposed between the stacked structures. The dielectric element is disposed between the channel element and the stacked structure. The source element is disposed between the upper surface of the substrate and the lower surface of the channel element. The bit line is disposed on the upper surface of the channel element. | 07-19-2012 |
20120184097 | Reduced Number of Masks for IC Device with Stacked Contact Levels - A three-dimensional stacked IC device has a stack of contact levels at an interconnect region. According to some examples of the present invention, it only requires a set of N etch masks to create up to and including 2N levels of interconnect contact regions at the stack of contact levels. According to some examples, 2 | 07-19-2012 |
20120185753 | Structure of ECC Spare Bits in 3D Memory - A structure of 3D memory comprises a plurality of stacking layers and a plurality of cells. The stacking layers are arranged in a three-dimensional array and disposed parallel to each other on a substrate, and the stacking layers comprises a plurality of stacking memory layers. The cells comprises a first group of cells (such as m of cells) for storing information data and a second group of cells (such as n of cells) for storing ECC (error checking and correcting) spare bits. All of the first group and the second group of cells are read out at the same time for performing an ECC function. The ECC spare bits in the 3D memory according to the present disclosure can be constructed at the same physical layer or at the different physical layers. The embodiments can be implemented, but not limited, by a vertical-gate (VG) structure or a finger VG structure. | 07-19-2012 |
20130075920 | Multilayer Connection Structure and Making Method - An IC device comprises a stack of contact levels, each including conductive layer and an insulation layer. A dielectric liner surrounds an interlevel conductor within an opening in the stack of contact levels. The opening passes through a portion of the stack of contact levels. The interlevel conductor is electrically insulated from the conductive layers of each of the contact levels through the dielectric liner. A portion of the conductive layer at the opening is recessed relative to adjacent insulation layers. The dielectric liner may have portions extending between adjacent insulation layers. | 03-28-2013 |
20130119457 | MEMORY DEVICE, MANUFACTURING METHOD AND OPERATING METHOD OF THE SAME - A memory device, a manufacturing method and an operating method of the same are provided. The memory device includes a substrate, stacked structures, a channel element, a dielectric element, a source element, and a bit line. The stacked structures are disposed on the substrate. Each of the stacked structures includes a string selection line, a word line, a ground selection line and an insulating line. The string selection line, the word line and the ground selection line are separated from each other by the insulating line. The channel element is disposed between the stacked structures. The dielectric element is disposed between the channel element and the stacked structure. The source element is disposed between the upper surface of the substrate and the lower surface of the channel element. The bit line is disposed on the upper surface of the channel element. | 05-16-2013 |
20130161835 | MULTILAYER CONNECTION STRUCTURE - A three-dimensional stacked IC device includes a stack of at least first, second, third and fourth contact levels at an interconnect region. Each contact level has a conductive layer and an insulation layer. First, second, third and fourth electrical conductors pass through portions of the stack of contact levels. The first, second, third and fourth electrical conductors are in electrical contact with the first, second, third and fourth conductive layers, respectively. A dielectric sidewall spacer circumferentially surrounds the second, third and fourth electrical conductors so that the second, third and fourth electrical conductors only electrically contact the respective second, third and fourth conductive layers. | 06-27-2013 |
20130214340 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME - A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first stacked structure, and a first conductive layer. The first stacked structure is formed on the substrate and includes a conductive structure and an insulating structure, and the conductive structure is disposed adjacent to the insulating structure. The first conductive layer is formed on the substrate and surrounds two side walls and a part of the top portion of the first stacked structure for exposing a portion of the first stacked structure. | 08-22-2013 |
20130264683 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME - A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a base, a stacked structure and a doped layer. The stacked structure is formed on the base, wherein the stacked structure comprises a plurality of conductive strips and a plurality of insulating strips, one of the conductive strips is located between adjacent two insulating strips, the stacked structure has a first side wall, and a long edge of the first side wall is extended along a channel direction. The doped layer is formed in the first side wall, wherein the doped layer is formed by an ion implantation applied to the first side wall, and an acute angle is contained between an implantation direction of the ion implantation and the first side wall. | 10-10-2013 |
20130264719 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure includes first and second chips assembled to each other. The first chip includes N of first conductive lines, M of second conductive lines disposed on the first conductive lines, N of third conductive lines perpendicularly on the second conductive lines and parallel to the first conductive lines, N of first vias connected to the first conductive lines, M sets of second vias connected to the second conductive lines, and N sets of third vias connected to the third conductive lines. The second and first conductive lines form an overlapping area. The third conductive lines and N sets of the third vias include at least two groups respectively disposed in a first and a third regions of the overlapping area. M sets of second vias include at least two groups respectively disposed in a second region and a fourth region of the overlapping area. | 10-10-2013 |
20130277799 | Integrated Circuit Capacitor and Method - An example of a capacitor includes a series of ridges and trenches and an interconnect region on the integrated circuit substrate. The series of ridges and trenches and the interconnect region have a capacitor foundation surface with a serpentine cross-sectional shape on the series of ridges and trenches. Electrical conductors are electrically connected to the electrode layers from the interconnect region for access to the electrode layers of the capacitor assembly. | 10-24-2013 |
20130277852 | Method for Creating a 3D Stacked Multichip Module - A 3D stacked multichip module comprises a stack of W IC die. Each die has a patterned conductor layer, including an electrical contact region with electrical conductors and, in some examples, device circuitry over a substrate. The electrical conductors of the stacked die are aligned. Electrical connectors extend into the stack to contact landing pads on the electrical conductors to create a 3D stacked multichip module. The electrical connectors may pass through vertical vias in the electrical contact regions. The landing pads may be arranged in a stair stepped arrangement. The stacked multichip module may be made using a set of N etch masks with 2 | 10-24-2013 |
20140043067 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD AND OPERATING METHOD OF THE SAME - A semiconductor structure and a manufacturing method and an operating method of the same are provided. The semiconductor structure includes a substrate, a main body structure, a first dielectric layer, a first conductive strip, a second conductive strip, a second dielectric layer, and a conductive structure. The main body structure is formed on the substrate, and the first dielectric layer is formed on the substrate and surrounding two sidewalls and a top portion of the main body structure. The first conductive strip and the second conductive strip are formed on two sidewalls of the first dielectric layer, respectively. The second dielectric layer is formed on the first dielectric layer, the first conductive strip, and the second conductive strip. The conductive structure is formed on the second dielectric layer. | 02-13-2014 |
20140053979 | REDUCED NUMBER OF MASKS FOR IC DEVICE WITH STACKED CONTACT LEVELS - A three-dimensional stacked IC device has a stack of contact levels at an interconnect region. According to some examples of the present invention, it only requires a set of N etch masks to create up to and including 2 | 02-27-2014 |
20140054535 | SEMICONDUCTOR STRUCTURE WITH IMPROVED CAPACITANCE OF BIT LINE - A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate. | 02-27-2014 |
20140061947 | CHIP STACK STRUCTURE AND MANUFACTURING METHOD THEREOF - A chip stack structure and a manufacturing method thereof are provided. The chip stack structure comprises a first chip, a second chip and a vertical conductive line. The second chip is disposed above the first chip. The vertical conductive line is electrically connected to the first chip and the second chip. The vertical conductive line is disposed at the outside of a projection area of the first chip and the second chip. | 03-06-2014 |
20140197516 | INTEGRATION OF 3D STACKED IC DEVICE WITH PERIPHERAL CIRCUITS - An integrated circuit device includes a substrate including a first region and a second region. A pit is formed in the first region. A stack of active layers alternating with insulating layers is deposited in the pit. The stack includes a particular insulating layer. The particular insulating layer has a first thickness, where a sum of the first thickness, thickness of active layers, and thicknesses of other insulating layers is essentially equal to a depth of the pit. The first thickness is different than the thicknesses of the other insulating layers by an amount within a range of process variations for the depth of the pit, for the thicknesses of the active layers, and for the thicknesses of other insulating layers. The device includes a planarized surface over the first and second regions, where an uppermost one of the active layers has a top surface below the planarized surface. | 07-17-2014 |
20140264925 | INTERLAYER CONDUCTOR AND METHOD FOR FORMING - A 3-D structure includes a stack of active layers at different depths has a plurality of contact landing areas on respective active layers within a contact area opening. A plurality of interlayer conductors, each includes a first portion within a contact area opening extending to a contact landing area, and a second portion in part outside the contact area opening above the top active layer. The first portion has a transverse dimension Y | 09-18-2014 |
20140264934 | INTERLAYER CONDUCTOR STRUCTURE AND METHOD - To form an interconnect conductor structure, a stack of pads, coupled to respective active layers of a circuit, is formed. Rows of interlayer conductors are formed to extend in an X direction in contact with landing areas on corresponding pads in the stack. Adjacent rows are separated from one another in a Y direction generally perpendicular to the X direction. The interlayer conductors in a row have a first pitch in the X direction. The interlayer conductors in adjacent rows are offset in the X direction by an amount less than the first pitch. Interconnect conductors are formed over and in contact with interlayer conductors. The interconnect conductors extend in the Y direction and have a second pitch less than the first pitch. | 09-18-2014 |
20140363922 | METHOD FOR CREATING A 3D STACKED MULTICHIP MODULE - A 3D stacked multichip module comprises a stack of W IC die. Each die has a patterned conductor layer, including an electrical contact region with electrical conductors and, in some examples, device circuitry over a substrate. The electrical conductors of the stacked die are aligned. Electrical connectors extend into the stack to contact landing pads on the electrical conductors to create a 3D stacked multichip module. The electrical connectors may pass through vertical vias in the electrical contact regions. The landing pads may be arranged in a stair stepped arrangement. The stacked multichip module may be made using a set of N etch masks with 2 | 12-11-2014 |
20150084203 | CONTACT STRUCTURE AND FORMING METHOD - A method for forming a contact structure includes forming a stack of alternating active layers and insulating layers. The stack includes first and second sub stacks each with active layers separated by insulating layers. The active layers of each sub stack include an upper boundary active layer. A sub stack insulating layer is formed between the first and second sub stacks with an etching time different from the etching times of the insulating layers for a given etching process. The upper boundary active layers are accessed, after which the remainder of the active layers are accessed to create a stairstep structure of landing areas on the active layers. Interlayer conductors are formed to extend to the landing areas, the interlayer conductors separated from one another by insulating material. | 03-26-2015 |