Patent application number | Description | Published |
20120037989 | LDMOS HAVING SINGLE-STRIP SOURCE CONTACT AND METHOD FOR MANUFACTURING SAME - LDMOS devices having a single-strip contact pad in the source region, and related methods of manufacturing are disclosed. The LDMOS may comprise a first well lightly doped with a first dopant and formed into a portion of a substrate, the first well having a drain region at its surface heavily doped with the first dopant, and a second well lightly doped with a second dopant formed in another portion of the substrate, the second well having a source region at its surface comprising first portions heavily doped with the first dopant directly adjacent second portions heavily doped with the second dopant. Also, the LDMOS device may comprise a field oxide at the upper surface of the substrate between the source and drain regions, and contacting the first well but separated from the second well, and a gate formed partially over the field oxide and partially over the source region. The LDMOS may also comprise contact pads in contact with the gate, and source and drain regions, wherein the contact pad in contact with the source regions comprises a single-strip of conductive material extending across the source region. | 02-16-2012 |
20120146139 | HIGH VOLTAGE SEMICONDUCTOR DEVICE - A semiconductor device for a high voltage application includes a doped source base region, an N+ source region, a P+ source region and a gate structure. The doped source base region has P-type. The N+ source region extends downwards into the doped source base region. The P+ source region is close to the N+ source region, extends downwards into the doped source base region, and is doped heavier than the doped source base region. The gate structure is coupled to the N+ source region and is near to the P+ source region. | 06-14-2012 |
20120270350 | SEMICONDUCTOR BIO-SENSORS AND METHODS OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor bio-sensor comprises providing a substrate, forming a first dielectric layer on the substrate, forming a patterned first conductive layer on the first dielectric layer, the patterned first conductive layer including a first portion and a pair of second portions, forming a second dielectric layer, a third dielectric layer and a fourth dielectric layer in sequence over the patterned first conductive layer, forming cavities into the fourth dielectric layer, forming vias through the cavities, exposing the second portions of the patterned first conductive layer, forming a patterned second conductive layer on the fourth dielectric layer, forming a passivation layer on the patterned second conductive layer, forming an opening to expose a portion of the third dielectric layer over the first portion of the patterned first conductive layer, and forming a chamber through the opening. | 10-25-2012 |
20130037883 | LDPMOS STRUCTURE FOR ENHANCING BREAKDOWN VOLTAGE AND SPECIFIC ON RESISTANCE IN BICMOS-DMOS PROCESS - An LDPMOS structure having enhanced breakdown voltage and specific on-resistance is described, as is a method for fabricating the structure. A P-field implanted layer formed in a drift region of the structure and surrounding a tightly doped drain region effectively increases breakdown voltage while maintaining a relatively low specific on-resistance. | 02-14-2013 |
20130056825 | MOS DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and method of forming the semiconductor device are disclosed, where the semiconductor device includes additional implant regions in the source and drain areas of the device for improving Ron-sp and BVD characteristics of the device. The device includes a gate electrode formed over a channel region that separates first and second implant regions in the device substrate. The first implant region has a first conductivity type, and the second implant region has a second conductivity type. A source diffusion region is formed in the first implant region, and a drain diffusion region is formed in the second implant region. | 03-07-2013 |
20130207236 | HIGH-BETA BIPOLAR JUNCTION TRANSISTOR AND METHOD OF MANUFACTURE - An NPN bipolar junction transistor is disclosed that exhibits a collector-to-emitter breakdown voltage greater than 10 volts and a beta greater than 300. The large value of beta is obtained by fabricating the transistor with an extra IN-type layer that reduces recombination of electrons and holes. | 08-15-2013 |
20140061721 | MOS DEVICE AND METHOD FOR FABRICATING THE SAME - An improved MOS device is provided whereby the p-top layer is defined by a series of discretely placed p type top diffusion regions. The invention also provides methods for fabricating the MOS device of the invention. | 03-06-2014 |
20140175547 | SEMICONDUCTOR DEVICE HAVING VARYING P-TOP AND N-GRADE REGIONS - An improved semiconductor is provided whereby n-grade and the p-top layers are defined by a series of discretely placed n-type and p-type diffusion segments. Also provided are methods for fabricating such a semiconductor. | 06-26-2014 |
20140197467 | HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR STRUCTURE - A JFET structure includes a first JFET having a first terminal and a second JFET neighboring with the first JFET. Both JFETs commonly share the first terminal and the first terminal is between the gate of each JFET. The JFET also provides at least one tuning knob to adjust the pinch-off voltage and a tuning knob to adjust the breakdown voltage of the JFET structure. Moreover, the JFET has a buried layer as another tuning knob to adjust the pinch-off voltage of the JFET structure. | 07-17-2014 |
20140302654 | MOS device and method of manufacturing the same - A semiconductor device and method of forming the semiconductor device are disclosed, where the semiconductor device includes additional implant regions in the source and drain areas of the device for improving Ron-sp and BVD characteristics of the device. The device includes a gate electrode formed over a channel region that separates first and second implant regions in the device substrate. The first implant region has a first conductivity type, and the second implant region has a second conductivity type. A source diffusion region is formed in the first implant region, and a drain diffusion region is formed in the second implant region. | 10-09-2014 |
20150048452 | ULTRA-HIGH VOLTAGE SEMICONDUCTOR HAVING AN ISOLATED STRUCTURE FOR HIGH SIDE OPERATION AND METHOD OF MANUFACTURE - A semiconductor device, in particular, an ultra-high metal oxide semiconductor (UHV MOS) device, is defined by a doped gradient structure in a drain region. For example, an ultra-high n-type metal oxide semiconductor (UHV NMOS) device is defined by an n-doped gradient structure in the drain region. The n-doped gradient structure has at least one of a high voltage n- (HVN-) well, a drain side high voltage n-type deep (HVND) well, and a drain side n-type well (NW) disposed in the drain region. A drain side n+ well is additionally disposed in the at least one of the HVN- well, the drain side HVND well, and the drain side NW. A method of manufacturing a UHV NMOS device having a doped gradient structure of a drain region is also provided. | 02-19-2015 |