Shibib
M. Ayman Shibib, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20160056138 | VERTICAL SENSE DEVICES IN VERTICAL TRENCH MOSFET - Vertical sense devices in vertical trench MOSFET. In accordance with an embodiment of the present invention, an electronic circuit includes a vertical trench metal oxide semiconductor field effect transistor configured for switching currents of at least one amp and a current sensing field effect transistor configured to provide an indication of drain to source current of the MOSFET. A current sense ratio of the current sensing FET is at least 15 thousand and may be greater than 29 thousand. | 02-25-2016 |
Muhammed Ayman Shibib, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20100123171 | Multi-level Lateral Floating Coupled Capacitor Transistor Structures - A semiconductor device includes a source region, a drain region, a gate region, and a drift region. The drift region further includes an active drift region and inactive floating charge control (FCC) regions. The active drift region conducts current between the source region and the drain region when voltage is applied to the gate region. The inactive FCC regions, which field-shape the active drift region to improve breakdown voltage, are vertically stacked in the drift region and are separated by the active drift region. Vertically stacking the inactive FCC regions reduce on-resistance while maintaining higher breakdown voltages. | 05-20-2010 |
20120211834 | MULTI-LEVEL LATERAL FLOATING COUPLED CAPACITOR TRANSISTOR STRUCTURES - A semiconductor device includes an active region having a first floating charge control structure and a termination region having a second floating charge control structure. The second floating charge control structure is at least twice as long as the first floating control structure. | 08-23-2012 |
Muhammed Ayman Shibib, Mountain View, CA US
Patent application number | Description | Published |
---|---|---|
20080296636 | Devices and integrated circuits including lateral floating capacitively coupled structures - According to the present invention, semiconductor device breakdown voltage can be increased by embedding field shaping regions within a drift region of the semiconductor device. A controllable current path extends between two device terminals on the top surface of a planar substrate, and the controllable current path includes the drift region. Each field shaping region includes two or more electrically conductive regions that are electrically insulated from each other, and which are capacitively coupled to each other to form a voltage divider dividing a potential between the first and second terminals. One or more of the electrically conductive regions are isolated from any external electrical contact. Such field shaping regions can provide enhanced electric field uniformity in current-carrying parts of the drift region, thereby increasing device breakdown voltage. Further aspects of the invention relate to device integration, efficient fabrication of field shaping regions and device isolation features using the same mask for both, and improved device structures. | 12-04-2008 |
Muhammed Ayman Shibib, Wyomissing, PA US
Patent application number | Description | Published |
---|---|---|
20120175702 | METAL-OXIDE-SEMICONDUCTOR DEVICE HAVING TRENCHED DIFFUSION REGION AND METHOD OF FORMING SAME - An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region. | 07-12-2012 |