Patent application number | Description | Published |
20100267232 | Transitional Interface Between Metal and Dielectric in Interconnect Structures - An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; an opening in the dielectric layer; a conductive line in the opening; a metal alloy layer overlying the conductive line; a first metal silicide layer overlying the metal alloy layer; and a second metal silicide layer different from the first metal silicide layer on the first metal silicide layer. The metal alloy layer and the first and the second metal silicide layers are substantially vertically aligned to the conductive line. | 10-21-2010 |
20100273324 | METHODS OF MANUFACTURING METAL-SILICIDE FEATURES - A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening. The metal-silicide layer may then be annealed. | 10-28-2010 |
20100314698 | METHODS OF MANUFACTURING METAL-SILICIDE FEATURES - A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening. The metal-silicide layer may then be annealed. | 12-16-2010 |
20110068466 | Wafer Backside Interconnect Structure Connected to TSVs - An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line. | 03-24-2011 |
20110241217 | Multi-Layer Interconnect Structure for Stacked Dies - A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements. | 10-06-2011 |
20120322261 | Methods for Via Structure with Improved Reliability - Methods for forming a via structure are provided. The method includes depositing a first-layer conductive line over a semiconductor substrate, forming a dielectric layer over the first-layer conductive line, forming a via opening in the dielectric layer and exposing the first-layer conductive line in the via opening, forming a recess portion in the first-layer conductive line, and filling the via opening to form a via extending through the dielectric layer to the first-layer conductive line. The via has a substantially tapered profile and substantially extends into the recess in the first-layer conductive line. | 12-20-2012 |
20130001799 | Multi-Layer Interconnect Structure for Stacked Dies - A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements. | 01-03-2013 |
20130334689 | APPARATUS AND METHOD FOR LOW CONTACT RESISTANCE CARBON NANOTUBE INTERCONNECT - An apparatus comprises a first dielectric layer formed over a substrate, a first metal line embedded in the first dielectric layer, a second dielectric layer formed over the first dielectric layer, a second metal line embedded in the second dielectric layer, an interconnect structure formed between the first metal line and the second metal line, a first carbon layer formed between the first metal line and the interconnect structure and a second carbon layer formed between the second metal line and the interconnect structure. | 12-19-2013 |
20140084471 | Interconnect Structures Comprising Flexible Buffer Layers - A structure includes a substrate, a low-k dielectric layer over the substrate, and a conductive barrier layer extending into the low-k dielectric layer. The conductive barrier layer includes a sidewall portion. A metal line in the low-k dielectric layer adjoins the conductive barrier layer. An organic buffer layer is between the sidewall portion of the conductive barrier layer and the low-k dielectric layer. | 03-27-2014 |
20140252618 | METHOD FOR FORMING INTERCONNECT STRUCTURE THAT AVOIDS VIA RECESS - A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. The dielectric material layer is patterned to form a plurality of vias therein. A first metal layer is formed on the dielectric material layer, wherein the first metal layer fills the plurality of vias. The first metal layer is planarized so that the top thereof is co-planar with the top of the dielectric material layer to form a plurality of first metal features. A stop layer is formed on top of each of the plurality of first metal features, wherein the stop layer stops a subsequent etch from etching into the plurality of the first metal features. | 09-11-2014 |
20140252622 | Method for Forming Recess-Free Interconnect Structure - A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. An oxygen-rich layer is formed over the dielectric material layer. The dielectric material layer and the oxygen-rich layer are patterned to form a plurality of vias in the semiconductor substrate. A barrier layer is formed in the plurality of vias and on the dielectric material layer leaving a portion of the oxygen-rich layer exposed. A metal layer is formed on the barrier layer and on the exposed portion of the oxygen-rich layer, wherein the metal layer fills the plurality of vias. The semiconductor substrate is annealed at a predetermined temperature range and at a predetermined pressure to transform the exposed portion of the oxygen-rich layer into a metal-oxide stop layer. | 09-11-2014 |
20140264908 | DUAL DAMASCENE GAP FILLING PROCESS - A method of forming a metallization layer in a semiconductor substrate includes forming a patterned dielectric layer on a substrate, the patterned dielectric layer having a plurality of first openings. A first conductive layer is formed in the plurality of first openings. A patterned mask layer is formed over portions of the first conductive layer outside the plurality of first openings, the patterned mask layer having a plurality of second openings, wherein at least a subset of the second openings are disposed over the first openings. A second conductive layer is filled in the plurality of second openings. The patterned mask layer is removed to leave behind the conductive layer structures on the substrate. The substrate is heated to form a self-forming barrier layer on the top and sidewalls of the conductive layer structures. | 09-18-2014 |
20140273434 | METHOD OF FABRICATING COPPER DAMASCENE - A method of fabricating a semiconductor device includes forming a non-conductive layer over a semiconductor substrate. A low-k dielectric layer is formed over the non-conductive layer. The low-k dielectric layer is etched and stopped at the non-conductive layer to form an opening. A plasma treatment is performed on the substrate to convert the non-conductive layer within the opening into a conductive layer. The opening is filled with a copper-containing material in an electroless copper bottom up fill process to form a copper-containing plug. The copper-containing plug is planarized so that the top of the copper-containing plug is co-planar with the top of the low-k dielectric layer. The substrate is heated to form a self-forming barrier layer on the sidewalls of the copper-containing plug. | 09-18-2014 |
20140312494 | Wafer Backside Interconnect Structure Connected to TSVs - An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line. | 10-23-2014 |
20140322909 | Wafer Backside Interconnect Structure Connected to TSVs - An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line. | 10-30-2014 |