Patent application number | Description | Published |
20110307770 | REDUCING A DEGREE OF A POLYNOMIAL IN A POLYNOMIAL DIVISION CALCULATION - An apparatus generally having a lookup table and a circuit is disclosed. The lookup table may be configured to store a plurality of results including remainders of divisions by a particular polynomial. The circuit may be configured to (i) parse a first polynomial into a plurality of data blocks and an end block, (ii) fetch a plurality of results from the lookup table by indexing the lookup table with each of the data blocks and (iii) generate a second polynomial by adding the results fetched from the lookup table to the end block. The second polynomial generally has a second degree that is lower that a first degree of the first polynomial. | 12-15-2011 |
20120102381 | SIMPLIFIED PARALLEL ADDRESS-GENERATION FOR INTERLEAVER - An apparatus including a first circuit and a second circuit. The first circuit may be configured to store a block of data values arranged in a first order. The first circuit may be further configured to present a plurality of the data values in parallel in response to a plurality of address signals, where the data values are presented in a second order. The second circuit may be configured to generate the plurality of address signals in response to a first signal, a second signal and a third signal. The second circuit generally includes an even number of address generators configured to generate the plurality of address signals in parallel. | 04-26-2012 |
20120157008 | METHOD FOR AVOIDING OVERFLOW OF MULTIPLICATION OF ROOTS-OF-UNITY BY USING OVERFLOW SAFE APPROXIMATED VALUES TABLE - An apparatus including a processor, a computer readable storage medium, and a lookup memory. The computer readable storage medium generally contains computer executable instruction that when executed by the processor perform operations involving fixed point multiplication. The lookup memory generally stores values used in the fixed point multiplication. The values stored in the lookup memory are approximated based upon a predetermined value to prevent overflow in the fixed point multiplication. | 06-21-2012 |
20120263246 | METHOD FOR REDUCING LATENCY ON LTE DL IMPLEMENTATION - An apparatus including a processor and a radio frequency (RF) interface. The processor may be configured to process downlink information such that a latency of the apparatus is determined by an amount of time involved in processing the downlink information to obtain a single orthogonal frequency division multiplexed (OFDM) symbol for presentation to the RF interface. | 10-18-2012 |
20120324316 | Turbo Parallel Concatenated Convolutional Code Implementation on Multiple-Issue Processor Cores - An iterative PCCC encoder includes a first delay line operative to receive at least one input data sample and to generate a plurality of delayed samples as a function of the input data sample. The encoder further includes a second delay line including a plurality of delay elements connected in a series configuration. An input of a first one of the delay elements is adapted to receive a sum of first and second signals, the first signal generated as a sum of the input data sample and at least one of the delayed samples, and the second signal generated as an output of a single one of the delay elements. A third delay line in the encoder is operative to generate an output data sample as a function of the sum of the first and second signals and a delayed version of the sum of the first and second signals. | 12-20-2012 |
20130022027 | DISCONTINUOUS TRANSMISSION IN A FRAME - An apparatus having a database and a circuit is disclosed. The database may be configured to store a plurality of entries. The circuit may be configured to (i) insert a plurality of indicators into a frame, (ii) generate the entries in the database and (iii) transmit the frame in response to the entries such that power is applied to an antenna corresponding to each of a plurality of data items in the frame and no power is applied to the antenna corresponding to each of the indicators in the frame. Each of the entries generally identifies a respective location in the frame. Each of the locations may begin a respective string comprising at least one of the indicators. | 01-24-2013 |
20130024489 | METHOD FOR FAST CALCULATION OF THE BEGINNING OF PSEUDO RANDOM SEQUENCES FOR LONG TERM EVOLUTION - An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate pseudo-random sequences in response to a first m-sequence and a second m-sequence, where the first m-sequence is initialized with a pre-calculated constant and the second m-sequence is initialized based on a pre-defined initial sequence and a table of pre-calculated values indicating which components of the initial sequence participate in initializing the second m-sequence. The second circuit may be configured to store the table of pre-calculated values. | 01-24-2013 |
20130077615 | INTERLEAVING FOR WIDEBAND CODE DIVISION MULTIPLE ACCESS - Described embodiments provide a wideband code division multiple access (W-CDMA) system, that employs an interleaving rule having a modified pruning algorithm. Interleaving, by pruning a sequence of bits in the W-CDMA system, includes determining a non-pruned interleaved vector having a length N. The determination of the non-pruned interleaved vector is based on a received length of an input vector from the sequence of bits. The input vector is padded. An interleaver generates a pre-pruned interleaved vector having a length equal to the length N, wherein the pre-pruned interleaved vector is a function of the padded input vector and the non-pruned interleaving vector. The interleaver prunes one or more elements from the pre-pruned interleaved vector based on a corresponding pruning indication in a pruning indication table, thereby providing a pruned interleaved vector as a portion of the interleaved sequence of bits. | 03-28-2013 |
20130102358 | MODULATION AND LAYER MAPPING IN PHYSICAL CHANNELS - Described embodiments provide a wireless communication system that employs modulation and precoding. An input bit stream is divided into one or more batches. Each batch has a consecutive number of bits. A modulation scheme is determined for batches. A precoding scheme for layer mapping is determined for the batches. Based on the modulation scheme and precoding scheme, a look-up table (LUT) is selected. The selected LUT maps the batches into one or more modulated and precoded layers. The modulated and precoded batches are provided to a transmission module. | 04-25-2013 |
20130182782 | INTERLEAVING, MODULATION, AND LAYER MAPPING IN AN LTE PHYSICAL CONTROL CHANNEL - In described embodiments, a physical downlink control channel of a device operating in accordance with a 3GPP LTE standard is processed to provide interleaving, modulation and multi-layer mapping and pre-coding. A Resource Element Group interleaver applies interleaving to an input signal representing an input bitstream, and a modulator modulates the input signal. After interleaving and modulating the signal, a multi-layer mapper and pre-coder layer-maps and pre-codes the interleaved and modulated input signal into a plurality of different layers. | 07-18-2013 |
20130188553 | DOWNLINK INDICATOR CHANNEL PROCESSING IN A WIRELESS SYSTEM BASE STATION - A transmitter comprises indicator channel processing circuitry configured to process indicator channel codewords for transmission in a base station of a wireless system. The indicator channel processing circuitry performs a plurality of processing operations on the indicator channel codewords in a specified processing sequence, with the plurality of processing operations comprising at least modulation, scrambling, spreading and combining. In the specified processing sequence, the scrambling operation is performed for at least a given one of the indicator channel codewords prior to the modulation and spreading operations for that codeword or subsequent to the combining operation for that codeword. For example, the specified processing sequence may comprise the scrambling, modulation, spreading and combining operations performed in that order for at least the given codeword, or the modulation, spreading, combining and scrambling operations performed in that order for at least the given codeword. | 07-25-2013 |
20130195021 | TABLE-BASED RESOURCE MAPPING FOR DOWNLINK CONTROL CHANNELS IN A WIRELESS SYSTEM BASE STATION - A transmitter comprises resource mapping circuitry configured to map symbols from multiple control channels to transmission symbols in a base station of a wireless system. The resource mapping circuitry comprises a table-based mapper configured to receive the control channel symbols and to map those symbols to the transmission symbols utilizing at least a selected one of a plurality of tables providing respective distinct mappings between the control channel symbols and the transmission symbols. For example, each of the transmission symbols may comprise a plurality of resource groups and the tables may specify distinct mappings of the control channels symbols to resource groups for different sets of possible base station parameter values. In one embodiment, the control channels comprise a physical control format indicator channel (PCFICH), a physical downlink control channel (PDCCH), and a physical hybrid ARQ indicator channel (PHICH) of an LTE cellular system. | 08-01-2013 |
20130223516 | BLOCK QUANTIZER IN H.264 WITH REDUCED COMPUTATIONAL STAGES - An apparatus including a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit may be configured to generate a first intermediate signal in response to a first input signal and a second input signal. The first intermediate signal generally comprises a product of the first input signal and the second input signal. The second circuit may be configured to generate a second intermediate signal by selecting between a first value and a second value in response to a sign of the first signal. The third circuit may be configured to generate a third intermediate signal in response to the first intermediate signal and the second intermediate signal. The third intermediate signal generally comprises a sum of the first intermediate signal and the second intermediate signal. The fourth circuit may be configured to generate an output signal in response to the third intermediate signal and a third input signal. | 08-29-2013 |