Patent application number | Description | Published |
20110254760 | Wireless Motion Processing Sensor Systems Suitable for Mobile and Battery Operation - The present invention relates to a combination of a 6-axis motion sensor having a 3-axis gyroscope and a 3-axis linear accelerometer, a motion processor and a radio integrated circuit chip (IC), wherein the intelligence in the motion processor enables the communication between the motion sensor, the radio IC and the external network. The motion processor also enables power savings by adaptively controlling the data rate of the motion sensor, depending on the amount or speed of the motion activity. | 10-20-2011 |
20120086446 | INTEGRATED MEMS DEVICE AND METHOD OF USE - An integrated MEMS device is disclosed. The system comprises a MEMS resonator; and a MEMS device coupled to a MEMS resonator. The MEMS resonator and MEMS device are fabricated on a common substrate so that certain characteristics of the MEM resonator and MEMS device track each other as operating conditions vary. | 04-12-2012 |
20120176128 | MICROMACHINED RESONANT MAGNETIC FIELD SENSORS - A micromachined magnetic field sensor comprising is disclosed. The micromachined magnetic field comprises a substrate; a drive subsystem, the drive subsystem comprises a plurality of beams, and at least one anchor connected to the substrate; a mechanism for providing an electrical current through the drive subsystem along a first axis; and Lorentz force acting on the drive subsystem along a second axis in response to a magnetic field along a third axis. The micromachined magnetic field sensor also includes a sense subsystem, the sense subsystem comprises a plurality of beams, and at least one anchor connected to the substrate; wherein a portion of the sense subsystem moves along a fourth axis; a coupling spring between the drive subsystem and the sense subsystem which causes motion of the sense subsystem in response to the magnetic field; and a position transducer to detect the motion of the sense subsystem. | 07-12-2012 |
20120176129 | MICROMACHINED RESONANT MAGNETIC FIELD SENSORS - A micromachined magnetic field sensor is disclosed. The micromachined magnetic field sensor comprises a substrate; and a drive subsystem partially supported by the substrate with a plurality of beams, and at least one anchor; a mechanism for providing an electrical current through the drive subsystem along a first axis; and Lorentz force acting on the drive subsystem along a second axis in response to a magnetic field vector along a third axis. The micromachined magnetic field sensor also includes a position transducer to detect the motion of the drive subsystem and an electrostatic offset cancellation mechanism coupled to the drive subsystem. | 07-12-2012 |
20120235670 | DRIVE SYSTEM FOR MICROMACHINED MAGNETIC FIELD SENSORS - Described herein are systems, devices, and methods that provide a stable magnetometer. The magnetometer includes a drive element that facilitates flow of a drive current through a node and a sense element operable to detect a magnetic field operating on the drive current. To reduce offset in the detection of the magnetic field, a voltage detector, electrically coupled to the drive element through the node, determines a variation between a node voltage and a target voltage. The voltage detector facilitates suppression of the variation and thereby minimizes the offset in the sense element. | 09-20-2012 |
20120242400 | HIGH-VOLTAGE MEMS APPARATUS AND METHOD - A high-voltage MEMS system compatible with low-voltage semiconductor process technology is disclosed. The system comprises a MEMS device coupled to a high-voltage bias generator employing an extended-voltage isolation residing in a semiconductor technology substrate. The system avoids the use of high-voltage transistors so that special high-voltage processing steps are not required of the semiconductor technology, thereby reducing process cost and complexity. MEMS testing capability is addressed with a self-test circuit allowing modulation of the bias voltage and current so that a need for external high-voltage connections and associated electro-static discharge protection circuitry are also avoided. | 09-27-2012 |
20120270511 | Closed Loop Power Control for a Wireless Transmitter - Embodiments of the present disclosure provide systems and methods for estimating gain and phase error in a wireless transmitter. Embodiments of the present disclosure provide a gain and phase controller that uses a digital gain and phase estimator to jointly estimate both gain and phase. The forward and feedback signals of a wireless transmitter are digitized using analog to digital (ADC) converters. The digital signals are correlated with each other to dynamically extract gain and phase estimates of the loop. The gain and phase estimates are used to correct gain and phase errors in the wireless transmitter. | 10-25-2012 |
20130099836 | GYROSCOPE WITH PHASE AND DUTY-CYCLE LOCKED LOOP - A system and method in accordance with the present invention provides a gyroscope incorporating an improved PLL technique. The improved PLL auto-corrects its own reference low-frequency noise, thereby eliminating this source of noise, improving the noise performance of the gyroscope and allowing a compact implementation. The net result is a gyroscope with improved bias stability that can meet noise requirements with a smaller footprint. | 04-25-2013 |
20130165058 | RF Transmitter Having Broadband Impedance Matching for Multi-Band Application Support - Systems and methods are provided for a broadband, closed-loop RF transmitter for multi-band applications that employs a single RE path to service multiple bands of operation. Embodiments of the present disclosure implement a broadband impedance matching module, which avoids the need for several costly and complex narrow-band matching networks. In an embodiment, the broadband impedance matching module includes concentric, mutually coupled inductors. By adding this broadband impedance matching functionality, delay is significantly reduced because a single path can be used to service multiple bands. | 06-27-2013 |
20140117966 | CURVATURE-CORRECTED BANDGAP REFERENCE - A curvature-corrected bandgap reference is disclosed. The curvature-corrected bandgap reference comprises a Brokaw bandgap circuit. The Brokaw bandgap circuit includes an output node providing a reference voltage. The Brokaw bandgap circuit further comprising a first BJT device including a first base terminal coupled to the output node and a first emitter terminal. The first BJT device operates at a first current density that is substantially proportional to absolute temperature. The curvature-corrected bandgap reference also includes a second BJT device including a second base terminal coupled to the output node and a second emitter terminal. The second BJT device operates at a second current density that is substantially independent of temperature. Finally the curvature-corrected bandgap reference includes a correction voltage proportional to a voltage difference of the first and second emitter terminals, wherein the correction voltage substantially cancels a curvature of the reference voltage. | 05-01-2014 |
20140141735 | RF Transmitter Having Broadband Impedance Matching for Multi-Band Application Support - Systems and methods are provided for a broadband, closed-loop RF transmitter for multi-band applications that employs a single RF path to service multiple bands of operation. Embodiments of the present disclosure implement a broadband impedance matching module, which avoids the need for several costly and complex narrow-band matching networks. In an embodiment, the broadband impedance matching module includes concentric, mutually-coupled inductors. By adding this broadband impedance matching functionality, delay is significantly reduced because a single path can be used to service multiple bands. | 05-22-2014 |
20140167789 | MODE-TUNING SENSE INTERFACE - A MEMS capacitive sensing interface includes a sense capacitor having a first terminal and a second terminal, and having associated therewith a first electrostatic force. Further included in the MEMS capacitive sensing interface is a feedback capacitor having a third terminal and a fourth terminal, the feedback capacitor having associated therewith a second electrostatic force. The second and the fourth terminals are coupled to a common mass, and a net electrostatic force includes the first and second electrostatic forces acting on the common mass. Further, a capacitance measurement circuit measures the sense capacitance and couples the first terminal and the third terminal. The capacitance measurement circuit, the sense capacitor, and the feedback capacitor define a feedback loop that substantially eliminates dependence of the net electrostatic force on a position of the common mass. | 06-19-2014 |
20140260619 | ROUND-ROBIN SENSING DEVICE AND METHOD OF USE - A round-robin sensing device is disclosed. The round-robin sensing device comprises a MEMS device, wherein the MEMS device includes first and second sense electrodes. The round-robin sensing device also comprises a multiplexer coupled to the first and second sense electrodes, at least one sense amplifier coupled to the multiplexer, a demodulator coupled to the at least one sense amplifier, and an integrate and dump circuit coupled to the demodulator. Finally, the round-robin sensing device comprises an analog-to-digital converter (ADC) coupled to the de-multiplexer, wherein the multiplexer, the at least one sense amplifier and the demodulator provide a continuous time sense path during amplification that is resettable and wherein the integrate and dump circuit and the ADC provide a discrete time processing path. | 09-18-2014 |
20140260647 | PRESSURE SENSOR STABILIZATION - A pressure sensor is provided which produces a measurement of the displacement and a measurement of a natural frequency of the diaphragm which are then combined to produce a compensated measurement of the displacement of the diaphragm, thereby substantially eliminating the dependence of the compensated displacement measurement on strain. | 09-18-2014 |
20140260713 | DUTY-CYCLED GYROSCOPE - A gyroscope system comprises a MEMS gyroscope coupled to a drive system and a sense system. The drive system maintains the MEMS gyroscope in a state of oscillation and the sense system for receiving, amplifying, and demodulating an output signal of the MEMS gyroscope that is indicative of the rate of rotation. The gyroscope system further includes a phase-locked look (PLL) which receives a reference clock (REFCLK) from the drive system and produces a system clock (CLK). Finally, the gyroscope system includes a controller operating on the system clock sets an operating state of the drive system and the sense system and also controls a state of the PLL. One or more system state variables are maintained in a substantially fixed state during a protect mode thereby enabling rapid transitions between a low-power mode and a normal operating mode of the gyroscope system. | 09-18-2014 |
20140266256 | LINEAR CAPACITIVE DISPLACEMENT SENSOR - A method and system for measuring displacement of a structure is disclosed. The method and system comprise providing a first capacitance and providing a second capacitance. The first and second capacitances share a common terminal. The method and system further include determining a difference of the inverses of the value of the first and second capacitances when the structure is displaced. The first capacitance varies in inverse relation to the displacement of the structure. | 09-18-2014 |
Patent application number | Description | Published |
20090198924 | Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device - Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization. | 08-06-2009 |
20100050010 | Data-Width Translation Between Variable-Width and Fixed-Width Data Ports - Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency. | 02-25-2010 |
20100146199 | Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device - Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization. | 06-10-2010 |
20110060875 | FRACTIONAL PROGRAM COMMANDS FOR MEMORY DEVICES - A memory system ( | 03-10-2011 |
20110228614 | Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device - Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization. | 09-22-2011 |
20120039139 | Memory Systems and Methods for Dividing Physical Memory Locations Into Temporal Memory Locations - Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency. | 02-16-2012 |
Patent application number | Description | Published |
20080315916 | CONTROLLING MEMORY DEVICES THAT HAVE ON-DIE TERMINATION - A memory controller for controlling integrated circuit memory devices that have on-die termination. The memory controller includes an output driver to output a first data signal onto a data line, and termination control circuitry to output termination control signals to integrated circuit memory devices coupled to the data line. The termination control signals control coupling and decoupling of termination elements to the data line according to which of the plurality of integrated circuit memory devices is selected to receive the first data signal. In particular, the termination control signals specify coupling a termination element having an impedance indicated by a first termination value to the data line within one of the plurality of integrated circuit memory devices selected to receive the first data signal, and wherein the termination control signals further specify coupling a termination element having an impedance indicated by a second termination value to the data line within at least one other of the plurality of integrated circuit memory devices. | 12-25-2008 |
20090130798 | Process for Making a Semiconductor System - Multiple devices, including a first device and a second device, have operational circuitry and opposing first and second surfaces. First and second electrical contacts are formed at the first surface, while a third electrical contact is formed at the second surface opposite the first electrical contact. The first electrical contact is electrically connected to the operational circuitry, and the second electrical contact is electrically connected to the third electrical contact. The first device and the second device are subsequently stacked such that the first surface of the second device is located adjacent the second surface of the first device such that the first electrical contact of the second device is aligned with the third electrical contact of the first device. The first electrical contact of the second device is electrically connected to the third electrical contact of the first device. | 05-21-2009 |
20090238025 | MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT - A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request. | 09-24-2009 |
20090284281 | MEMORY-MODULE BUFFER WITH ON-DIE TERMINATION - In memory module having multiple data inputs to couple to signal lines of an external data path, multiple memory integrated-circuits (ICs) and a buffer IC, the buffer IC includes respective interfaces coupled to the data inputs and the memory ICs, a first termination circuit having a first load element and a first switch element to switchably couple the first load element to a first data input of the data inputs and a second termination circuit having a second load element and a second switch element to switchably couple the second load element to the first data input. The buffer IC further includes a configuration circuit to store, in response to control information from a memory controller, a first digital value and a second digital value, the first digital value being supplied to the first termination circuit to control an impedance of the first load element and the second digital value being supplied to the second termination circuit to control an impedance of the second load element. | 11-19-2009 |
20100027356 | Dynamic On-Die Termination of Address and Command Signals - A system includes a plurality of memory devices arranged in a fly-by topology, each of the memory devices having on-die termination (ODT) circuitry for connection to an address and control (RQ) bus. The ODT circuitry has at least one input for controlling termination of one or more signal lines of the RQ bus. Application of a first logic level to the at least one input enables termination of the one or more signal lines. Application of a second logic level to the at least one input disables termination of the one or more signal lines. | 02-04-2010 |
20100039875 | Strobe Acquisition and Tracking - A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command if a time interval since a last read command issued by the memory controller exceeds a predetermined value. | 02-18-2010 |
20100315122 | MEMORY CONTROLLER THAT CONTROLS TERMINATION IN A MEMORY DEVICE - A memory controller that controls termination in a memory device. The memory controller includes a data interface, command/address interface and termination control output. The data interface outputs write data onto a data line coupled to a data input of the memory device, and the command/address interfaces outputs, onto a command/address path coupled to the memory device, information that indicates whether the write data is to be received within the memory device. The termination control output asserts a first termination control signal on a termination control signal line coupled to the memory device to cause the memory device to either (i) couple a first termination impedance to the data line while the write data is present at the data input of the memory device if the information indicates that the write data is to be received within the memory device, or (ii) couple a second termination impedance to the data line while the write data is present at the data input of the memory device if the information indicates that the write data is not to be received within the memory device. | 12-16-2010 |
20110156750 | INTEGRATED CIRCUIT DEVICE WITH DYNAMICALLY SELECTED ON-DIE TERMINATION - In an integrated circuit device having dynamically selected on-die termination, a set of data inputs are coupled respectively to a set of termination circuits, each termination circuit having multiple controllable termination impedance configurations. A termination control signal input is provided to receive an indication that the integrated circuit device is to apply one of the controllable termination impedance configurations at each of the data inputs, and a logic circuit applies one of a first and a second of the controllable termination impedance configurations at the data inputs based on the indication received at the termination control signal input and an internal state of the memory device, such that during a first internal state corresponding to the reception of write data on the data inputs, the first of the controllable termination impedance configurations is applied at each of the data inputs, and during a second internal state following the first internal state, the second of the controllable termination impedance configurations is applied at each of the data inputs. | 06-30-2011 |
20110241727 | DYNAMIC ON-DIE TERMINATION SELECTION - In an integrated circuit device having dynamically selected on-die termination, a set of data inputs are coupled respectively to a set of termination circuits, each termination circuit having multiple controllable termination impedance configurations. A termination control signal input is provided to receive an indication that the integrated circuit device is to apply one of the controllable termination impedance configurations at each of the data inputs, and a logic circuit applies one of a first and a second of the controllable termination impedance configurations at the data inputs based on the indication received at the termination control signal input and an internal state of the memory device, such that during a first internal state corresponding to the reception of write data on the data inputs, the first of the controllable termination impedance configurations is applied at each of the data inputs, and during a second internal state following the first internal state, the second of the controllable termination impedance configurations is applied at each of the data inputs. | 10-06-2011 |
20110248407 | Process For Making a Semiconductor System - Multiple devices, including a first device and a second device, have operational circuitry and opposing first and second surfaces. First and second electrical contacts are formed at the first surface, while a third electrical contact is formed at the second surface opposite the first electrical contact. The first electrical contact is electrically connected to the operational circuitry, and the second electrical contact is electrically connected to the third electrical contact. The first device and the second device are subsequently stacked such that the first surface of the second device is located adjacent the second surface of the first device such that the first electrical contact of the second device is aligned with the third electrical contact of the first device. The first electrical contact of the second device is electrically connected to the third electrical contact of the first device. | 10-13-2011 |
20110267101 | CONTROLLING DYNAMIC SELECTION OF ON-DIE TERMINATION - A control component outputs to an integrated circuit device an indication to apply one of a plurality of controllable termination impedance configurations at a data input of the integrated circuit device. The indication causes the integrated circuit device to apply a first of the controllable termination impedance configurations at the data input during a first internal state of the integrated circuit device corresponding to the reception of write data on the data input, and causes the integrated circuit device to apply a second of the controllable termination impedance configurations at the data input during a second internal state of the integrated circuit device that follows the first internal state. | 11-03-2011 |
20120188835 | INTEGRATED CIRCUIT WITH STAGGERED SIGNAL OUTPUT - A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request. | 07-26-2012 |
20120265930 | CONTROLLING ON-DIE TERMINATION IN A DYNAMIC RANDOM ACCESS MEMORY DEVICE - An integrated circuit device transmits, to a dynamic random access memory device (DRAM), a write command indicating that write data is to be sampled by a data interface of the DRAM, and a plurality of commands that specify programming a plurality of control values into a plurality of corresponding registers in the DRAM. The plurality of control values include first and second control values that indicate respective first and second terminations that the DRAM is to apply to the data interface during a time interval that begins a predetermined amount of time after the DRAM receives the write command, the first termination to be applied during a first portion of the time interval while the data interface is sampling the write data and the second termination to be applied during a second portion of the time interval after the write data is sampled. | 10-18-2012 |
20140329359 | PROCESS FOR MAKING A SEMICONDUCTOR SYSTEM - Multiple devices, including a first device and a second device, have operational circuitry and opposing first and second surfaces. First and second electrical contacts are formed at the first surface, while a third electrical contact is formed at the second surface opposite the first electrical contact. The first electrical contact is electrically connected to the operational circuitry, and the second electrical contact is electrically connected to the third electrical contact. The first device and the second device are subsequently stacked such that the first surface of the second device is located adjacent the second surface of the first device such that the first electrical contact of the second device is aligned with the third electrical contact of the first device. The first electrical contact of the second device is electrically connected to the third electrical contact of the first device. | 11-06-2014 |
Patent application number | Description | Published |
20110138133 | Variable-Width Memory Module and Buffer - A memory module having a plurality of memory devices and a memory buffer that translates between a variable width primary data port and a plurality of fixed width secondary data ports, each of which is coupled to one of the memory devices. The translation is effected by distributing the width of the primary data port to all or to a subset of the secondary data ports. In another aspect, the invention comprises a memory buffer that supports adjustable data width in a variety of ways. | 06-09-2011 |
20110299317 | INTEGRATED CIRCUIT HEATING TO EFFECT IN-SITU ANNEALING - In a system having a memory device, an event is detected during system operation. The memory device is heated to reverse use-incurred degradation of the memory device in response to detecting the event. In another system, the memory device is heated to reverse use-incurred degradation concurrently with execution of a data access operation within another memory device of the system. In another system having a memory controller coupled to first and second memory devices, data is evacuated from the first memory device to the second memory device in response to determining that a maintenance operation is needed within the first memory device. | 12-08-2011 |
20130111176 | MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT | 05-02-2013 |
20130148447 | Reducing Power Consumption in a Memory System - Components of a memory system, such as a memory controller or memory device, that operate in different power states to reduce the overall power consumption of the memory system. In some of the power states, distribution circuitry that distributes a timing signal within the components may be powered on when the output of the distribution circuitry is needed. In other power states, the distribution circuitry may be powered off when the output of the distribution circuitry is not needed. Additionally, power states in the memory device may be triggered off memory access commands issued by the memory controller. | 06-13-2013 |
20130201770 | MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION - Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated. | 08-08-2013 |
20130254585 | CLOCK GENERATION FOR TIMING COMMUNICATIONS WITH RANKS OF MEMORY DEVICES - A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device. | 09-26-2013 |
20130307584 | MULTI-VALUED ON-DIE TERMINATION - An integrated circuit memory device stores a plurality of digital values that specify respective termination impedances. The memory device switchably couples respective sets of load elements to a data input/output (I/O) to apply the termination impedances specified by the digital values, including, applying a first termination impedance to the data I/O during an idle state of the memory device, applying a first one of two non-equal termination impedances to the data I/O while the memory device receives write data in a memory write operation and applying a second one of the two non-equal termination impedances to the data I/O while another memory device receives write data in a memory write operation. When outputting read data via the data I/O in a memory read operation, the memory device switchably couples to the data I/O at least a portion of the load elements included in the sets of load elements. | 11-21-2013 |
20140016423 | Reducing Memory Refresh Exit Time - Components of a memory system, such as a memory controller and a memory device, that reduce delay in exiting self-refresh mode by controlling the refresh timing of the memory device. The memory device includes a memory core. An interface circuit of the memory device receives an external refresh signal indicating an intermittent refresh event. A refresh circuit of the memory device generates an internal refresh signal indicating an internal refresh event of the memory device. A refresh control circuit of the memory device performs a refresh operation on a portion of the memory core responsive to the internal refresh event, at a time relative to the intermittent refresh event indicated by the external refresh signal. | 01-16-2014 |
20140108889 | MEMORY SYSTEM FOR ERROR DETECTION AND CORRECTION COVERAGE - A memory system supporting error detection and correction (EDC) coverage. The system includes a memory controller and a memory buffer. The memory buffer includes an interface to a first group of memory devices and an interface to a second group of memory devices. The memory buffer accesses data from the first group of memory devices and accesses first error information corresponding to the data from the second group of devices. The memory buffer also accesses additional data from the second group of memory devices and accesses second error information corresponding to the additional data from a device in the first group of memory devices. EDC coverage may also be configured by the memory controller so that some data accesses have EDC coverage and other data accesses do not have EDC coverage. | 04-17-2014 |
20140140149 | Strobe Acquisition and Tracking - A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value. | 05-22-2014 |
20140164823 | Memory Disturbance Recovery Mechanism - Components of a memory system, such as a memory controller and memory device, which detect accumulated memory read disturbances and correct such disturbances before they reach a level that causes errors. The memory device includes a memory array and a disturbance control circuit. The memory array includes a plurality of memory rows. Each memory row is associated with a disturbance warning circuit having a state that corresponds to an accumulated disturbance in the memory row. The disturbance control circuit determines, responsive to an activation of a memory row of the plurality of memory rows specified by a row access command, whether the disturbance condition is present in the memory row based on the state of the disturbance warning circuit associated with the memory row. If a disturbance condition is present, the disturbance control circuit causes a recovery operation to be performed on the memory row to reduce the accumulated disturbances. | 06-12-2014 |
20140173240 | MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT - A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request. | 06-19-2014 |
20140281205 | MEMORY CIRCUIT AND METHOD FOR ITS OPERATION - In an illustrative embodiment, the memory circuit includes first and second data paths on which data is transferred for read and write memory operations and first and second mixer circuits for adjusting the phase of clock signals applied to their inputs. The mixer circuits are cross-coupled so that the outputs of the first and second mixers are both available to both the first and second data paths. One mixer is used to provide a first phase adjusted clock signal for use by the operating circuit and the other mixer is used to provide a second phase adjusted clock signal for use by a following operation whatever that may be. | 09-18-2014 |
20150016046 | INA CABLED MEMORY APPLIANCE - According to one general aspect, an apparatus may include an expansion memory device, a connection printed circuit board, and a connection cable. The expansion memory device may include a plurality of memory chips. The connection printed circuit board may be configured to be physically coupled with a memory socket. The connection cable may be configured to electrically couple the connection printed circuit board with the expansion memory device and transmit electrical signals therebetween. | 01-15-2015 |
20150042378 | BUFFERED MEMORY MODULE HAVING MULTI-VALUED ON-DIE TERMINATION - In a memory module having an integrated-circuit buffer device coupled to one or more integrated-circuit memory devices, the buffer device receives write data signals from an external control component via a set of data inputs, the write data signals indicating write data to be stored within one or more of the memory devices. Logic within the buffer device sequentially applies controllable termination impedance configurations at the data inputs based on an indication received from the control component and an internal state of the buffer device, applying a first controllable termination impedance configuration at each of the data inputs during a first internal state of the buffer device corresponding to the reception of the write data signals on the data inputs, and applying a second controllable termination impedance configuration at each of the data inputs during a second internal state of the buffer device that succeeds the first internal state. | 02-12-2015 |
20150084672 | COMMAND-TRIGGERED ON-DIE TERMINATION - An integrated circuit device transmits to a dynamic random access memory (DRAM) one or more commands that specify programming of a digital control value within the DRAM, the digital control value indicating a termination impedance that the DRAM is to couple to a data interface of the DRAM in response to receiving a write command and during reception of write data corresponding to the write command, and that the DRAM is to decouple from the data interface after reception of the write data corresponding to the write command. Thereafter, the integrated circuit device transmits to the DRAM a write command indicating that write data is to be sampled by a data interface of the DRAM during a first time interval and that cause the DRAM to couple the termination impedance to the data interface during the first time interval and decouple the termination impedance from the data interface after the first time interval. | 03-26-2015 |