Patent application number | Description | Published |
20130016089 | IMAGE DISPLAY DEVICEAANM Kim; JooahAACI SeoulAACO KRAAGP Kim; Jooah Seoul KRAANM Hwang; KwangjoAACI Anyang-siAACO KRAAGP Hwang; Kwangjo Anyang-si KRAANM Kim; EuitaeAACI Goyang-siAACO KRAAGP Kim; Euitae Goyang-si KRAANM Park; JoonyoungAACI Paju-siAACO KRAAGP Park; Joonyoung Paju-si KRAANM Baek; SeunghoAACI Paju-siAACO KRAAGP Baek; Seungho Paju-si KRAANM Kim; JeongkiAACI Paju-siAACO KRAAGP Kim; Jeongki Paju-si KR - An image display device includes a display panel which selectively displays a 2D image and a 3D image and includes a plurality of pixels, a patterned retarder for dividing light from the display panel into first polarized light and second polarized light, and a control voltage generation circuit which generates a 2D control voltage at an off-level and generates a 3D control voltage alternately having a slight-on level and the off-level every predetermined period of time. The slight-on level is higher than the off-level and is lower than a full-on level. Each pixel includes a main display unit including a first pixel electrode and a first common electrode and a subsidiary display unit including a second pixel electrode, a second common electrode, and a discharge control switch. | 01-17-2013 |
20130033480 | STEREOSCOPIC IMAGE DISPLAY - A a stereoscopic image display includes: a liquid crystal display panel including a 3D control line to which a 3D control voltage is applied, and a plurality of pixels, each of the pixels being divided into a main pixel portion and an active black stripe; and a 3D control voltage generation circuit that supplies a 3D control voltage to the 3D control line and discharges a voltage of the active black stripe down to a black gray voltage. | 02-07-2013 |
20130057533 | STEREOSCOPIC IMAGE DISPLAY - A stereoscopic image display includes a display panel which includes a plurality of pixels each including a main display unit and an auxiliary display unit, is divided into a first screen block and a second screen block, and includes a first discharge control line connected to auxiliary display units of the first screen block and a second discharge control line connected to auxiliary display units of the second screen block, a control voltage generator which generates a first discharge control voltage of a first AC waveform and a second discharge control voltage of a second AC waveform, of which a phase is later than a phase of the first AC waveform by a half frame period, and a control voltage delay unit which delays the first and second discharge control voltages. | 03-07-2013 |
20130088654 | STEREOSCOPIC IMAGE DISPLAY - A stereoscopic image display includes a liquid crystal display panel including a plurality of pixels, each of which is divided into a main pixel unit and an switchable black stripe, a data driving circuit, a gate driving circuit, and a 3D control voltage generation circuit, which supplies AC voltages, of which phases are sequentially shifted, to a plurality of 3D control lines in a 3D mode. | 04-11-2013 |
20130100181 | DIGITAL HOLOGRAM IMAGE REPRODUCING DEVICE AND SYNCHRONIZATION CONTROL METHOD THEREOF - A digital hologram image reproducing device includes a light modulator reproducing a hologram interference fringe image, a first panel driving circuit which scans a first display panel and writes data of the hologram interference fringe image to the first display panel, a first timing controller controlling an operation timing of the first panel driving circuit, a second panel driving circuit which scans a second display panel and writes data of the hologram interference fringe image to the second display panel, a second timing controller controlling an operation timing of the second panel driving circuit, and a panel synchronization circuit which simultaneously transfers a polarity control signal received from one of the first and second timing controllers to the first and second panel driving circuits. | 04-25-2013 |
20130235019 | STEREOSCOPIC IMAGE DISPLAY - The stereoscopic image display includes a control voltage generator and a control voltage compensator. The control voltage generator generates a discharge control voltage to be applied to a discharge control line at a slight-on level, which is higher than a gate low voltage and is lower than a gate high voltage, and periodically reduces the discharge control voltage to a level of the gate low voltage in the 3D mode. The control voltage compensator receives the discharge control voltage from the control voltage generator, amplifies a feedback discharge control voltage supplied from a first part of a display panel based on the received discharge control voltage, and applies the amplified feedback discharge control voltage, as a compensated discharge control voltage, to a second part opposite the first part of the display panel. | 09-12-2013 |
20140071120 | MEMORY REDUCTION DEVICE OF STEREOSCOPIC IMAGE DISPLAY FOR COMPENSATING CROSSTALK - A memory reduction device of a stereoscopic image display includes a compression unit configured to receive first to fourth input data belonging to Gn and comprised of K1 bit, respectively, align the first to fourth input data in order of a data size to generate first to fourth alignment data, generate first to fourth compression data groups including first and second compression data having K2 bits smaller than K1 bits and third compression data having K3 bits smaller than K2 bits based on the first to fourth alignment data, derive an outlier from the first to fourth input data by using a deviation between the first to fourth alignment data, select any one of the first to fourth compression data groups, as the compressed Gn−1 according to the presence or absence of the outlier and an outlier derivation position. | 03-13-2014 |
Patent application number | Description | Published |
20100191523 | Method and apparatus for recovering line spectrum pair parameter and speech decoding apparatus using same - A method and an apparatus for recovering a line spectrum pair (LSP) parameter of a spectrum region when frame loss occurs during speech decoding and a speech decoding apparatus adopting the same are provided. The method of recovering an LSP parameter in speech decoding includes: if it is determined that a received speech packet has an erased frame, converting an LSP parameter of a previous good frame (PGF) of the erased frame or LSP parameters of the PGF and a next good frame (NGF) of the erased frame into a spectrum region and obtaining a spectrum envelope of the PGF or spectrum envelopes of the PGF and NGF; recovering a spectrum envelope of the erased frame using the spectrum envelope of the PGF or the spectrum envelopes of the PGF and NGF; and converting the recovered spectrum envelope of the erased frame into an LSP parameter of the erased frame. The method and apparatus can improve the quality of a recovered speech signal, be applied to a variety of technologies, and provide a method of recovering an LSP parameter for development of an algorithm for speech decoding. | 07-29-2010 |
20120232888 | APPARATUS AND METHOD FOR CONCEALING FRAME ERASURE AND VOICE DECODING APPARATUS AND METHOD USING THE SAME - An apparatus and method for concealing frame erasure and a voice decoding apparatus and method using the same. The frame erasure concealment apparatus includes: a parameter extraction unit determining whether there is an erased frame in a voice packet, and extracting an excitement signal parameter and a line spectrum pair parameter of a previous good frame; and an erasure frame concealment unit, if there is an erased frame, restoring the excitement signal and line spectrum pair parameter of the erased frame by using a regression analysis from the excitement signal and line spectrum pair parameter of the previous good frame. According to the method and apparatus, by predicting and restoring the parameter of the erased frame through the regression analysis, the quality of the restored voice signal can be enhanced and the algorithm can be simplified. | 09-13-2012 |
20130275127 | APPARATUS AND METHOD FOR CONCEALING FRAME ERASURE AND VOICE DECODING APPARATUS AND METHOD USING THE SAME - An apparatus and method for concealing frame erasure and a voice decoding apparatus and method using the same. The frame erasure concealment apparatus includes: a parameter extraction unit determining whether there is an erased frame in a voice packet, and extracting an excitement signal parameter and a line spectrum pair parameter of a previous good frame; and an erasure frame concealment unit, if there is an erased frame, restoring the excitement signal and line spectrum pair parameter of the erased frame by using a regression analysis from the excitement signal and line spectrum pair parameter of the previous good frame. According to the method and apparatus, by predicting and restoring the parameter of the erased frame through the regression analysis, the quality of the restored voice signal can be enhanced and the algorithm can be simplified. | 10-17-2013 |
20160111101 | APPARATUS AND METHOD FOR CONCEALING FRAME ERASURE AND VOICE DECODING APPARATUS AND METHOD USING THE SAME - An apparatus and method for concealing frame erasure and a voice decoding apparatus and method using the same. The frame erasure concealment apparatus includes: a parameter extraction unit determining whether there is an erased frame in a voice packet, and extracting an excitement signal parameter and a line spectrum pair parameter of a previous good frame; and an erasure frame concealment unit, if there is an erased frame, restoring the excitement signal and line spectrum pair parameter of the erased frame by using a regression analysis from the excitement signal and line spectrum pair parameter of the previous good frame. According to the method and apparatus, by predicting and restoring the parameter of the erased frame through the regression analysis, the quality of the restored voice signal can be enhanced and the algorithm can be simplified. | 04-21-2016 |
Patent application number | Description | Published |
20140195555 | AUTOMATIC REPORT GENERATION IN A NETWORKED COMPUTING ENVIRONMENT - An approach for automatically generating reports in a networked computing environment is provided. Specifically, in a typical embodiment, a user will: designate and/or modify a report template; input a set of unique identifiers corresponding to a set of electronic documents (e.g., patent documents); optionally designate a hierarchy of the set of electronic documents; provide a set of input parameters for report content; and optionally provide any manually generated content. Thereafter, the electronic documents will be retrieved from a database or the like. Based on the input parameters, report content and/or report objects will be automatically generated from the electronic documents and populated into a report (using the template) along with the manually generated content provided by the user. | 07-10-2014 |
20140201193 | INTELLECTUAL PROPERTY ASSET INFORMATION RETRIEVAL SYSTEM - An approach for automatically retrieving information corresponding to intellectual property (IP) assets in a networked computing environment is provided. In general, a user will submit search input (e.g., keywords, patent numbers, etc.), that is used to search an intellectual property databases (e.g., USPTO) to generate a set of matching results. IP identifier information will then be extracted from the set of results and matched against a set of tables containing deterministic (e.g., legal/litigation) information corresponding to a set of IP assets (e.g., patents, trademarks, copyrights, etc.). Any deterministic information corresponding to IP assets that match the IP identifier information extracted from the set of results may then be outputted for the user. Thus, the user may see any deterministic information that corresponds to an IP asset in which the user may be interested. | 07-17-2014 |
20140214699 | MANAGING INTELLECTUAL PROPERTY ASSET TRANSACTION INFORMATION IN A NETWORKED COMPUTING ENVIRONMENT - A set of computer storage devices containing transaction records having transaction information corresponding to a set of transactions for a set of IP assets will be queried. At least a subset of the transaction information will be extracted and the types of IP transactions will be determined. A first table will then be generated based on the extracted transaction information. The first table typically identifies each IP transaction and corresponding transaction information. Based on the transaction information, a most recent transaction record for each of the set of IP assets will be identified. The system will then generate a second table based on the transaction information and the types of IP transaction(s). The second table will identify the most recent transaction information for each of the set of IP assets. | 07-31-2014 |
20140223293 | AUTOMATIC REPORT GENERATION IN A NETWORKED COMPUTING ENVIRONMENT - An approach for automatically generating reports in a networked computing environment is provided. In a typical embodiment, the system will receive a set of unique identifiers associated with a set of IP assets and a set of input parameters in a computer memory medium. A (customizable) template will then be designated/selected for a report for the set of IP assets. The template will typically have at least one automatically generated portion and at least one manually generated portion. A set of IP documents corresponding to the set of IP assets will be identified using the set of unique identifiers. This allows information to be extracted from the set of IP documents. The template will then be populated (e.g., according to the input parameters) using the extracted information, a set of analysis content, and any manually provided content. | 08-07-2014 |
Patent application number | Description | Published |
20140097888 | MULTI-VOLTAGE SUPPLIED INPUT BUFFER - An input buffer capable of interfacing higher-voltage logic signals to lower voltage internal circuitry includes a first stage configured to generate a first output signal in response to an input signal, the first stage configured to receive a first power supply voltage and including semiconductor circuit components configured to be variably biased responsive to a variable voltage. The input buffer also includes a second stage configured to receive the first output voltage and to responsively generate a second output signal, the second stage biased according to the first power supply voltage. The input buffer further includes a bias circuit configured to generate the variable voltage responsive to a state of the input signal. | 04-10-2014 |
20140320657 | Camera Module for Vehicle - A camera module for a vehicle according to the present invention includes a first Printed Circuit Board (PCB) configured to have an image sensor mounted on its surface; a second PCB configured to supply a power source to the first PCB; an outer shield installed to surround the side of the first and the second PCBs and to shield the first and the second PCBs from electromagnetic interference (EMI); and a plurality of support units disposed at positions where the supports units interfere with the first and the second PCBs of the outer shield and configured to support the first and the second PCBs. | 10-30-2014 |
20140354814 | Pop-Up Type Camera Module for Vehicle and Method of Controlling Appearance and Disappearance of the Camera Module - A pop-up type vehicle camera unit according to the present invention includes a camera module; a cover member installed in the rear of the camera module and configured to protect the camera module; a driving motor configured to have one end coupled to the cover member and to rotate the cover member while operating in conjunction with forward rotation and backward rotation operations; and a control unit configured to detect a power source supplied to the camera module, forward rotate the driving motor so that the camera module pops up when the power source supplied to the camera module is turned on, and backward rotates the driving motor so that the camera module is hidden when the power source supplied to the camera module is turned off, wherein the pop-up type camera unit is installed at least one of a front grill and a rear garnish of the vehicle. | 12-04-2014 |
20150189137 | CAMERA MODULE FOR VEHICLE - A camera module for a vehicle according to the present invention includes a first Printed Circuit Board (PCB) configured to have an image sensor mounted on its surface; a second PCB configured to supply a power source to the first PCB; an outer shield installed to surround the side of the first and the second PCBs and to shield the first and the second PCBs from electromagnetic interference (EMI); and a plurality of support units disposed at positions where the supports units interfere with the first and the second PCBs of the outer shield and configured to support the first and the second PCBs. | 07-02-2015 |
20160061511 | REFRIGERATOR - A refrigerator includes a cabinet having a storage chamber, a main door pivotably mounted to the cabinet while including an opening provided at an inside of the main door, and a stepped portion provided around the opening, a sub-storage chamber mounted at the inside of the main door, a sub-door mounted to the main door, to allow a user to have access to the sub-storage chamber, the sub-door having opposite side surfaces with front portions protruding forwards of a front surface of the main door while having a greater width than the opening and stepped portion between the front portions of the side surfaces, to cover the stepped portion by the side surfaces, and a hinge pivotably mounted to the main door and coupled to the sub-door while being bent at an intermediate portion thereof, to pivotably support the sub-door with respect to the main door. | 03-03-2016 |
20160134064 | REFRIGERATOR - The present invention discloses a refrigerator including a refrigerator main body having an opening, a door connected to the refrigerator main body and configured to open and close the opening, a storage unit configured to be moved toward a rear wall within the refrigerator main body so as to be installed in the refrigerator main body, the rear wall facing the opening, a power supply unit mounted at the rear wall and having an accommodating portion formed to face the opening, and a connection unit mounted at the storage unit, wherein when the storage unit is moved to the rear wall and installed in the refrigerator main body, at least part of the connection unit is inserted into the accommodating portion so as to be electrically connected to the power supply unit. | 05-12-2016 |
Patent application number | Description | Published |
20100082890 | Method of managing a solid state drive, associated systems and implementations - A solid state drive may include one or more memory cell arrays divided into a plurality of blocks. A first portion of the blocks may be designated for storing user data and a second portion of the blocks may be designated as reserved blocks for replacing defective blocks in the first portion. In one embodiment, the method includes reformatting, by a memory controller, the solid state drive to convert one or more blocks in the first portion into reserved blocks. | 04-01-2010 |
20100293319 | Solid state drive device - The solid state drive device includes a memory device including a plurality of flash memories and a memory controller connected with a host and configured to control the memory device. The memory controller includes first and second cores, a host interface configured to interface with the host, and a flash memory controller configured to control the plurality of flash memories. The first core is configured to control transmission and reception of data to and from the host. The second core is configured to control transmission and reception of data to and from the memory device. | 11-18-2010 |
20110191649 | SOLID STATE DRIVE AND METHOD OF CONTROLLING AN ERROR THEREOF - The present general inventive concept relates to a solid state drive and a method of controlling an error thereof. A flash translation layer includes a parity managing module to correct errors. A block address of a storage medium including error data that can be recovered is managed through the parity managing module. Parity data of a block including error data is generated through the parity managing module. The generated parity data is managed through the parity managing module. The generated parity data can be stored in an assigned area of the storage medium. When data of a block managed by the parity managing module is not recovered by an error correction code unit, error data is recovered with reference to the generated parity data. | 08-04-2011 |
20110238900 | Method of managing a solid state drive, associated systems and implementations - In one embodiment, the method includes storing, by a status checking module, status information for a solid state drive, and determining a status state of the solid state drive based on the status information. The status state is one of a good state, an intermediate state and a bad state, and the intermediate state is a state between the good state and the bad state. | 09-29-2011 |
20110238971 | Method of managing a solid state drive, associated systems and implementations - One embodiment of a method includes loading, by a memory controller, a boot image from a solid state drive to an operating memory of a computing system during an initialization operation of the computing system. The initialization operation initializes components of the computing system. | 09-29-2011 |
20150026449 | METHOD OF MANAGING A SOLID STATE DRIVE, ASSOCIATED SYSTEMS AND IMPLEMENTATIONS - One embodiment of a method includes loading, by a memory controller, a boot image from a solid state drive to an operating memory of a computing system during an initialization operation of the computing system. The initialization operation initializes components of the computing system. | 01-22-2015 |
20150058546 | SOLID STATE DRIVE DEVICE - The solid state drive device includes a memory device including a plurality of flash memories and a memory controller connected with a host and configured to control the memory device. The memory controller includes first and second cores, a host interface configured to interface with the host, and a flash memory controller configured to control the plurality of flash memories. The first core is configured to control transmission and reception of data to and from the host. The second core is configured to control transmission and reception of data to and from the memory device. | 02-26-2015 |
20150248242 | SOLID STATE DRIVE DEVICE - The solid state drive device includes a memory device including a plurality of flash memories and a memory controller connected with a host and configured to control the memory device. The memory controller includes first and second cores, a host interface configured to interface with the host, and a flash memory controller configured to control the plurality of flash memories. The first core is configured to control transmission and reception of data to and from the host. The second core is configured to control transmission and reception of data to and from the memory device. | 09-03-2015 |