Patent application number | Description | Published |
20080209092 | METHOD AND SYSTEM FOR INTERFACING A PLURALITY OF MEMORY DEVICES USING AN MMC/SD PROTOCOL - A method for establishing an interface between a host and a plurality of memory devices of a system that utilizes a Multimedia Card (MMC)/Secure Digital (SD) protocol according to an interleaving scheme. A host sequentially transmits a first sequence of commands and data to a system bus in order to allow a first memory device among the memory devices to perform a first operation. The host then transmits a second sequence of commands and data to the system bus to allow a second memory device among the memory devices to perform a second operation after transmitting the first sequence of commands and data. | 08-28-2008 |
20090049268 | PORTABLE STORAGE DEVICE AND METHOD OF MANAGING RESOURCE OF THE PORTABLE STORAGE DEVICE - Provided are a portable storage device and a method of managing a resource of the portable storage device. The method includes converting a first DRM application into a ready status from an idle status if task processing of the first DRM application is required, and converting the first DRM application into a pending status and a second DRM application into the ready status from the idle status if task processing of the second DRM application is required. | 02-19-2009 |
20110083039 | MEMORY SYSTEMS AND METHODS OF DETECTING DISTRIBUTION OF UNSTABLE MEMORY CELLS - A circuit is operated to detect unstable memory cells from among a plurality of memory cells in at least one page. A determination is made from an initial status of data stored in a memory cell whether no read error occurs when the data is read at a standard read voltage level, whether a read error occurs and the read error is correctable, and whether a read error occurs and the read error is uncorrectable. Responsive to determining that a read error occurs that is correctable, a further determination is made as to whether the memory cell is correctable by reading the data stored in the memory cell at a correction read voltage level, which has a different voltage level from the standard read voltage level, and by determining whether a read error occurring in the data read at the correction read voltage level is correctable or uncorrectable. | 04-07-2011 |
20110219180 | FLASH MEMORY DEVICE WITH MULTI-LEVEL CELLS AND METHOD OF WRITING DATA THEREIN - In one aspect, a method of writing data in a flash memory system is provided. The flash memory system forms an address mapping pattern according to a log block mapping scheme. The method includes determining a writing pattern of data to be written in a log block, and allocating one of SLC and MLC blocks to the log block in accordance with the writing pattern of the data. | 09-08-2011 |
20120159054 | FLASH MEMORY DEVICE WITH MULTI-LEVEL CELLS AND METHOD OF WRITING DATA THEREIN - In one aspect, a method of writing data in a flash memory system is provided. The flash memory system forms an address mapping pattern according to a log block mapping scheme. The method includes determining a writing pattern of data to be written in a log block, and allocating one of SLC and MLC blocks to the log block in accordance with the writing pattern of the data. | 06-21-2012 |
20130173857 | FLASH MEMORY DEVICE WITH MULTI-LEVEL CELLS AND METHOD OF WRITING DATA THEREIN - In one aspect, a method of writing data in a flash memory system is provided. The flash memory system forms an address mapping pattern according to a log block mapping scheme. The method includes determining a writing pattern of data to be written in a log block, and allocating one of SLC and MLC blocks to the log block in accordance with the writing pattern of the data. | 07-04-2013 |
20140379970 | FLASH MEMORY DEVICE WITH MULTI-LEVEL CELLS AND METHOD OF WRITING DATA THEREIN - In one aspect, a method of writing data in a flash memory system is provided. The flash memory system forms an address mapping pattern according to a log block mapping scheme. The method includes determining a writing pattern of data to be written in a log block, and allocating one of SLC and MLC blocks to the log block in accordance with the writing pattern of the data. | 12-25-2014 |