Patent application number | Description | Published |
20090213659 | FLASH MEMORY DEVICE AND FLASH MEMORY SYSTEM INCLUDING THE SAME - A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit. | 08-27-2009 |
20090316483 | Flash memory device and system including the same - The invention provides an operation method of a memory system including a flash memory device. The method includes programming at least one page included in a selected memory block of the flash memory device; and determining the selected memory block or the flash memory device to be invalid, according to whether a loop number of the programmed page is out of a reference loop range. | 12-24-2009 |
20100008149 | FLASH MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A programming method of a flash memory device having memory cells, and a flash memory device to perform the method, including programming selected memory cells according to loaded data, sensing states of the programmed memory cells and firstly latching the sensed states, and determining whether a program-inhibited memory cell among the selected memory cells has been programmed, with reference to the loaded data and the latched states, before determining whether the selected memory cells have been properly programmed. | 01-14-2010 |
20110090740 | NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A flash memory device comprises alternately arranged odd and even memory cells. The odd and even memory cells are connected to corresponding odd and even bitlines, which are connected to corresponding odd and even page buffers. In a read operation of the flash memory device, data is sensed at two different times via the odd and even bitlines. In certain embodiments, data is read from the odd page buffers while data is being sensed via the even bit lines, or vice versa. | 04-21-2011 |
20110255338 | Flash memory device and system including the same - The invention provides an operation method of a memory system including a flash memory device. The method includes programming at least one page included in a selected memory block of the flash memory device; and determining the selected memory block or the flash memory device to be invalid, according to whether a loop number of the programmed page is out of a reference loop range. | 10-20-2011 |
20120221880 | MEMORY SYSTEM AND METHOD OF CONTROLLING SAME - A memory system comprises a controller that generates a processor clock, and a plurality of memory devices each comprising an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times. | 08-30-2012 |
20130028025 | NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A flash memory device comprises alternately arranged odd and even memory cells. The odd and even memory cells are connected to corresponding odd and even bitlines, which are connected to corresponding odd and even page buffers. In a read operation of the flash memory device, data is sensed at two different times via the odd and even bitlines. In certain embodiments, data is read from the odd page buffers while data is being sensed via the even bit lines, or vice versa. | 01-31-2013 |
20140036594 | NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A flash memory device comprises alternately arranged odd and even memory cells. The odd and even memory cells are connected to corresponding odd and even bitlines, which are connected to corresponding odd and even page buffers. In a read operation of the flash memory device, data is sensed at two different times via the odd and even bitlines. In certain embodiments, data is read from the odd page buffers while data is being sensed via the even bit lines, or vice versa. | 02-06-2014 |