Semiconductor Manufacturing
Semiconductor Manufacturing International (beijing) Corporation US
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20140077277 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate that has a surface. The semiconductor further includes a fin disposed on the surface and including a semiconductor member. The semiconductor further includes a spacer disposed on the surface, having a type of stress, and overlapping the semiconductor member in a direction parallel to the surface. A thickness of the spacer in a direction perpendicular to the surface is less than a height of the semiconductor member in the direction perpendicular to the surface. | 03-20-2014 |
Semiconductor Manufacturing International Corporation, Shanghai CN
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20130082015 | ELASTIC RETENTION WHEELS AND WAFER ADAPTER CONTAINING THE SAME WHEELS - An elastic retention wheel and a wafer adapter containing this wheel are disclosed. The elastic retention wheel comprises: a rim; a retention main body positioned within the rim; and a plurality of spokes. Each spoke is positioned in a space between the rim and the retention main body. One end of each spoke is coupled to the retention main body, and the other end is coupled to the rim. A sliding rail can be provided on an inner side of the rim, and the spoke's other end can slide with the sliding rail. When the elastic retention wheel is stressed by a non-uniform or excessive external force, these spokes provide enhanced support from the rim's inner side, or at least partially disperse the non-uniform external force applied to the elastic retention wheel. Thereby, the elastic retention wheel is largely kept from over-deformation or cracking. | 04-04-2013 |
20130168872 | VIA ARRANGEMENT AND SEMICONDUCTOR DEVICE WITH THE VIA ARRANGEMENT - A semiconductor device may include a first line of vias including a first via and a second via immediately adjacent to the first via. The semiconductor device may further include a second line of vias arranged immediately adjacent to and parallel to the first line of vias, the second line of vias including a third via immediately adjacent to the first via and the second via, the second line of vias further including a fourth via immediately adjacent to the third via, the first via, and the second via. The shortest distance between the second via and the fourth via may be greater than the shortest distance between the first via and the second via. | 07-04-2013 |
20130171742 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a miniaturized semiconductor device so as to form MTJ elements therein include the steps of depositing a magnetic tunnel junction (MTJ) precursor layer on a substrate and planarizing the precursor layer; forming a sacrificial and patternable dielectric layer on the MTJ precursor layer; patterning the sacrificial dielectric layer in accordance with predetermined placements and shapes of a to-be-formed hard mask, the patterning forming corresponding openings in the sacrificial dielectric layer; depositing an etch-resistant conductive material such as Cu in the openings for example by way of plating, and selectively removing the sacrificial dielectric layer so as to leave behind the etch-resistant conductive material in the form of a desired hard mask. Using the hard mask to etch and thus pattern the MTJ precursor layer so as to form MTJ elements having desired locations, sizes and shapes. | 07-04-2013 |
Semiconductor Manufacturing International Corporation (beijing), Beijing CN
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20130168741 | COMPLEMENTARY JUNCTION FIELD EFFECT TRANSISTOR DEVICE AND ITS GATE-LAST FABRICATION METHOD - The disclosure relates to a complementary junction field effect transistor (c-JFET) and its gate-last fabrication method. The method of fabricating a semiconductor device includes: forming a dummy gate on a first conductivity type wafer, forming sidewall spacers on opposite sides of the dummy gate, forming a source and a drain regions on the opposite sides of the dummy gate, removing the dummy gate, forming a first semiconductor region of a second conductivity type in an opening exposed through the removing the dummy gate, and forming a gate electrode in the opening. | 07-04-2013 |
20130168861 | ELECTRICALLY CONDUCTIVE DEVICE AND MANUFACTURING METHOD THEREOF - An electrically conductive device and a manufacturing method thereof are provided. According to the method, a protein tube portion and a conductor penetrating through the protein tube portion are formed on a graphene layer, and the conductor is in electrical contact with the graphene layer. A dummy dielectric material layer surrounding the protein tube portion can be formed on the graphene layer for support. The graphene layer can be protected from damage during the formation of the protein tube portion and the conductor because no etching process is employed in the formation. The method can facilitate the application of graphene in semiconductor devices as conductive interconnects. | 07-04-2013 |
Semiconductor Manufacturing International (shangai) Corporation US
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20130228833 | SYSTEM AND METHOD FOR INTEGRATED CIRCUITS WITH CYLINDRICAL GATE STRUCTURES - A device and method for integrated circuits with surrounding gate structures are disclosed. The device includes a semiconductor substrate and a fin structure on the semiconductor substrate. The fin structure is doped with a first conductivity type and includes a source region at one distal end and a drain region at the opposite distal end. The device further includes a gate structure overlying a channel region disposed between the source and drain regions of the fin structure. The fin structure has a rectangular cross-sectional bottom portion and an arched cross-sectional top portion. The arched cross-sectional top portion is semi-circular shaped and has a radius that is equal to or smaller than the height of the rectangular cross-sectional bottom portion. The source, drain, and the channel regions each are doped with dopants of the same polarity and the same concentration. | 09-05-2013 |