Patent application number | Description | Published |
20090019225 | INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING SYSTEM - With respect to memory access instructions contained in an internal representation program, an information processing apparatus generates a load cache instruction, a cache hit judgment instruction, and a cache miss instruction that is executed in correspondence with a result of a judgment process performed according to the cache hit judgment instruction. In a case where the internal representation program contains a plurality of memory access instruction having a possibility of using mutually the same cache line in a cache memory when mutually different cache lines in a main memory are accessed, the information processing apparatus generates a combine instruction instructing that judgment results of the judgment processes that are performed according to the cache hit judgment instruction should be combined into one judgment result. The information processing apparatus outputs an output program that contains these instructions that have been generated. | 01-15-2009 |
20090019266 | INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING SYSTEM - With respect to memory access instructions contained in an internal representation program, an information processing apparatus generates a load cache instruction, a cache hit judgment instruction, and a cache miss instruction that is executed in correspondence with a result of a judgment process performed according to the cache hit judgment instruction. In a case where the internal representation program contains a plurality of memory access instructions having a possibility of causing accesses to mutually the same cache line in a cache memory, the information processing apparatus generates a combine instruction instructing that judgment results of the judgment processes that are performed according to the cache hit judgment instruction should be combined into one judgment result. The information processing apparatus outputs an output program that contains these instructions that have been generated. | 01-15-2009 |
20100100685 | EFFECTIVE ADDRESS CACHE MEMORY, PROCESSOR AND EFFECTIVE ADDRESS CACHING METHOD - An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process, and output a hit signal when the effective page tag matches the effective page tag from a processor; a data memory configured to retain cache data with the effective page tag or a page offset as a cache index; and a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the cache index. | 04-22-2010 |
20100235607 | PROCESSOR - A processor includes a setting register in which a mode is set, a general-purpose register including a preferred slot used during scalar computing and a slot not used during the scalar computing, a selector configured to select and output data of a register designated by a mode set in the setting register during the scalar computing, and a computing unit configured to execute the scalar computing using the preferred slot of the general-purpose register and store computing result data of the scalar computing in the preferred slot of the general-purpose register. The data of the register output from the selector is stored in the slot of the general-purpose register. | 09-16-2010 |
20110055647 | PROCESSOR - A processor has an ALU, a load/store unit, a timer, an ECC calculator, and a plurality of ECC registers. When the load/store unit writes data in a main memory, the load/store unit writes written data and a count value of a timer in the main memory, and sets ECC status flag which indicates that an ECC about the written data is not correct in the main memory, and causes the ECC calculator to calculate the ECC about the written data after setting the ECC status flag, and writes the calculated ECC in the main memory and resets the ECC status flag after the ECC is calculated. | 03-03-2011 |
20110099336 | CACHE MEMORY CONTROL CIRCUIT AND CACHE MEMORY CONTROL METHOD - A cache memory control circuit has a plurality of counters, each of which is provided per set and per memory space and configured to count how many pieces of data of a corresponding memory space is stored in a corresponding set. The cache memory control circuit controls activation of a tag memory and a data memory of each of a plurality of sets according to a count value of each of the plurality of counters. | 04-28-2011 |
20110231593 | VIRTUAL ADDRESS CACHE MEMORY, PROCESSOR AND MULTIPROCESSOR - An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address. | 09-22-2011 |
20140164702 | VIRTUAL ADDRESS CACHE MEMORY, PROCESSOR AND MULTIPROCESSOR - An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address. | 06-12-2014 |
20150081752 | MATRIX OPERATION APPARATUS - According to an embodiment, a matrix operation apparatus executing a matrix operation includes multiple nodes, the nodes including: a multiplier configured to perform a first operation for a first input, which is column data and a second input which is row data for the matrix operation and output element components of an operation result of the matrix operation; and an accumulator configured to perform cumulative addition of operation results of the multiplier. | 03-19-2015 |