Patent application number | Description | Published |
20080283926 | METHOD FOR INTEGRATING SILICON GERMANIUM AND CARBON DOPED SILICON WITHIN A STRAINED CMOS FLOW - The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes providing a substrate having a PMOS device region and NMOS device region. Thereafter, a first gate structure and a second gate structure are formed over the PMOS device region and the NMOS device region, respectively. Additionally, recessed epitaxial SiGe regions may be formed in the substrate on opposing sides of the first gate structure. Moreover, first source/drain regions may be formed on opposing sides of the first gate structure and second source/drain regions on opposing sides of the second gate structure. The first source/drain regions and second source/drain regions may then be annealed to form activated first source/drain regions and activated second source/drain regions, respectively. Additionally, recessed epitaxial carbon doped silicon regions may be formed in the substrate on opposing sides of the second gate structure after annealing. | 11-20-2008 |
20080283935 | TRENCH ISOLATION STRUCTURE AND METHOD OF MANUFACTURE THEREFOR - The disclosure provides a trench isolation structure, a semiconductor device, and a method for manufacturing a semiconductor device. The semiconductor device, in one embodiment, includes a substrate having a first device region and a second device region, wherein the first device region includes a first gate structure and first source/drain regions and the second device region includes a second gate structure and second source/drain regions. The semiconductor device further includes a trench isolation structure configured to isolate the first device region from the second device region, the trench isolation structure comprising: 1) an isolation trench located within the substrate, wherein the isolation trench includes an opening portion and a bulbous portion, and further wherein a maximum width of the opening portion is less than a maximum width of the bulbous portion, and 2) dielectric material substantially filling the isolation trench. | 11-20-2008 |
20080283936 | SILICON GERMANIUM FLOW WITH RAISED SOURCE/DRAIN REGIONS IN THE NMOS - Provided is a method for manufacturing a semiconductor device that includes a substrate having a PMOS device region and NMOS device region. A first gate structure including a first hardmask and a second gate structure including a second hardmask are formed in the region and region, respectively. Epitaxial SiGe regions are created in the substrate proximate the first gate structure, the first hardmask protecting the first gate structure from the SiGe. First source/drain regions are formed proximate the first gate structure, at least a portion of each of the first source/drain regions located within one of the SiGe regions. Additionally, a raised portion is grown above the substrate proximate the second gate structure, the portion forming at least a part of second source/drain regions located on opposing sides of the second gate structure. Additionally, the first and second hardmasks protect the first and second gate structures from the growing. | 11-20-2008 |
20090042377 | METHOD FOR FORMING SELF-ALIGNED WELLS TO SUPPORT TIGHT SPACING - Methods include utilizing a single mask layer to form tightly spaced, adjacent first-type and second-type well regions. The mask layer is formed over a substrate in a region in which the second-type well regions will be formed. The first-type well regions are formed in the exposed portions of the substrate. Then, the second-type well-regions are formed through the resist mask. | 02-12-2009 |
20090256199 | LATERAL METAL OXIDE SEMICONDUCTOR DRAIN EXTENSION DESIGN - A semiconductor device comprising source and drain regions and insulating region and a plate structure. The source and drain regions are on or in a semiconductor substrate. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a thin layer and a thick layer. The thick layer includes a plurality of insulating stripes that are separated from each other and that extend across a length between the source and the drain regions. The plate structure is located between the source and the drain regions, wherein the plate structure is located on the thin layer and portions of the thick layer, the plate structure having one or more conductive bands that are directly over individual ones of the plurality of insulating stripes. | 10-15-2009 |
20090258471 | Application of Different Isolation Schemes for Logic and Embedded Memory - The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic. | 10-15-2009 |
20090280618 | Method of Planarizing a Semiconductor Device - A process of forming a semiconductor process fabricated device which contains a trench, hole or gap filled with a conformally deposited material is disclosed. A sacrificial planarizing layer is formed on the fill material, and the device is planarized using a selective RIE process which etches the fill material faster than the sacrificial planarizing layer. An overetch step completes the planarization process. | 11-12-2009 |
20100163998 | TRENCH ISOLATION COMPRISING PROCESS HAVING MULTIPLE GATE DIELECTRIC THICKNESSES AND INTEGRATED CIRCUITS THEREFROM - A method of fabricating an integrated circuit (IC) including a first plurality of MOS transistors having a first gate dielectric having a first thickness in first regions, and a second plurality of MOS transistors having a second gate dielectric having a second thickness in second regions, wherein the first thickness07-01-2010 | |
20100164004 | METHODS FOR REDUCING GATE DIELECTRIC THINNING ON TRENCH ISOLATION EDGES AND INTEGRATED CIRCUITS THEREFROM - A method of fabricating an integrated circuit (IC) including a plurality of MOS transistors and ICs therefrom include providing a substrate having a silicon including surface, and forming a plurality of dielectric filled trench isolation regions in the substrate, wherein the silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. A first silicon including layer is deposited, wherein the first silicon including extends from a surface of the trench isolation regions over the trench isolation active area edges to the silicon including surface. The first silicon including layer is completely oxidized to convert the first silicon layer to a silicon oxide layer, wherein the silicon oxide layer provides at least a portion of a gate dielectric for at least one of the plurality of MOS transistors. A patterned gate electrode layer is formed over the gate dielectric, wherein the patterned gate electrode layer extends over at least one of the trench isolation active area edges to the silicon including surface, and fabrication is then completed. | 07-01-2010 |
20100224937 | METHOD FOR INTEGRATING SILICON GERMANIUM AND CARBON DOPED SILICON WITHIN A STRAINED CMOS FLOW - The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes providing a substrate ( | 09-09-2010 |
20100314670 | STRAINED LDMOS AND DEMOS - An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the <100> direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the <110> direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing a p-channel extended drain MOS transistor with drift region current flow oriented in a <110> direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa tensile stress. | 12-16-2010 |
20110076822 | LATERAL METAL OXIDE SEMICONDUCTOR DRAIN EXTENSION DESIGN - A semiconductor device | 03-31-2011 |
20120100679 | THICK GATE OXIDE FOR LDMOS AND DEMOS - A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage transistors, replacing the dummy oxide in the low voltage transistor area with a thinner gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor. A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage and intermediate voltage transistors, replacing the dummy oxide in the low voltage transistors with a thinner gate dielectric layer, replacing the dummy oxide in the intermediate voltage transistor with another gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor. | 04-26-2012 |
20130105909 | HIGH VOLTAGE CMOS WITH TRIPLE GATE OXIDE | 05-02-2013 |
20140183662 | DEEP TRENCH ISOLATION WITH TANK CONTACT GROUNDING - An integrated circuit is formed on a substrate containing a semiconductor material having a first conductivity type. A deep well having a second, opposite, conductivity type is formed in the semiconductor material of the first conductivity type. A deep isolation trench is formed in the substrate through the deep well so as separate an unused portion of the deep well from a functional portion of the deep well. The functional portion of the deep well contains an active circuit element of the integrated circuit. The separated portion of the deep well does not contain an active circuit element. A contact region having the second conductivity type and a higher average doping density than the deep well is formed in the separated portion of the deep well. The contact region is connected to a voltage terminal of the integrated circuit. | 07-03-2014 |
20140220761 | REDUCTION OF POLYSILICON RESIDUE IN A TRENCH FOR POLYSILICON TRENCH FILLING PROCESSES - A method of fabricating a semiconductor device includes forming at least one trench from a top side of a semiconductor layer, wherein the trench is lined with a trench dielectric liner and filled by a first polysilicon layer. The surface of the trench dielectric liner is etched, wherein dips in the trench dielectric liner are formed relative to a top surface of the first polysilicon layer which results in forming a protrusion including the first polysilicon layer. The first polysilicon layer is etched to remove at least a portion of the protrusion. A second dielectric layer is formed over at least the trench after etching the first polysilicon layer. A second polysilicon layer is deposited. The second polysilicon layer is etched to remove it over the trench and provide a patterned second polysilicon layer on the top side of the semiconductor layer. | 08-07-2014 |