Patent application number | Description | Published |
20080265993 | Class AB Rail-to-Rail Input and Output Operational Amplifier - An operational amplifier including an input stage. The input stage may include first and second differential input circuits and a first current mirror. When an input terminal of the operational amplifier is at a positive voltage rail, the first differential input circuit may be activated. When the input terminal is at a negative voltage rail, the second differential input circuit may be activated. In either case, this may cause the first current mirror to provide a current of a predetermined value to each of first and second input terminals of a control circuit, and to each of first and second nodes coupled to a rail-to-rail output stage. The input stage may maintain the current provided to each of the input terminals of the control circuit and to each of the nodes coupled to the rail-to-rail output stage constant over the full input voltage range from the negative voltage rail to the positive voltage rail. | 10-30-2008 |
20090009234 | Proportional Settling Time Adjustment For Diode Voltage And Temperature Measurements Dependent On Forced Level Current - A temperature sensor circuit and system providing accurate digital temperature readings using a local or remote temperature diode. In one set of embodiments a change in diode junction voltage (ΔV | 01-08-2009 |
20090220219 | Delta-Sigma Modulator for a Fan Driver - A fan driver circuit for powering a fan with a linear voltage may be designed using digital design techniques, resulting in a testable, accurate circuit on a smaller die size. The fan driver circuit may be configured to receive a digital control signal, which may be a sequence of numeric values, e.g. multiple-bit binary numbers, each indicative of a desired present rotational speed of the fan. The fan driver circuit may be implemented using a digital modulator, e.g. a delta-sigma modulator, with a simple low-pass filter, e.g. an RC-filter at the output, and may use oversampling based on a system clock, to shift in-band noise to out-of-band frequencies, and digital interpolation to filter out unwanted images from the upsampled digital control signal. The delta-sigma modulator may be constructed as a first-order delta-sigma modulator using an error-feedback structure to reduce die size. | 09-03-2009 |
20090237117 | ELECTRICAL PHYSICAL LAYER ACTIVITY DETECTOR - A low-current differential signal activity detector circuit may be configured to reject large common mode signals on differential input lines, while still detecting smaller differential signals applied to the same set of differential input lines. The detector circuit may comprise a translinear buffer that is driven at the buffer input and at the buffer output by the differential input signals. The differential signal thereby driving the inputs of the detector circuit may be half-wave rectified through the buffer output devices and may be filtered to provide the detected output. When applying a common mode signal, the buffer's input and output may track each other, and no current may be rectified in the output devices, thus providing common-mode signal rejection. The detector circuit may also be configured with two buffers having their outputs coupled to a common node, each buffer input driven by a respective one of the differential input signals. The differential signal thereby driving the inputs of the detector circuit may be fully rectified through the output devices of the two buffers, and may be filtered to provide the detected output. The two buffers may be configured in a symmetrical structure that allows for the rejection of common-mode signals when the outputs of the buffers are coupled to a common node. | 09-24-2009 |
20090322351 | Adaptive Capacitive Sensing - A capacitive sensing circuit may comprise an RC (resistive-capacitive) bridge circuit, with a switching signal simultaneously applied to a reference path, and a signal path comprising the capacitance to be detected. Small perturbations in the capacitance may be detected by mixing/correlating a difference signal representative of the difference between the reference path signal and the signal path signal, to the switching signal. The output of the mixer may be filtered to virtually eliminate all EMI signals. A narrowband approach may also allow filtering of unwanted signals, enabling operation in systems susceptible to high levels of noise. Frequency stepping of the switching signal may minimize inband signal interference, and allow operation in the presence of many signals that would otherwise result in failure of the sensing circuit. Pad calibration may be implemented to free the user from a need to characterize each button channel capacitance and tailor the operation for each channel. | 12-31-2009 |
20100213917 | Frequency Compensation Scheme for Stabilizing the LDO Using External NPN in HV Domain - A voltage regulator may comprise a regulator output configured to provide a regulated voltage, which may be controlled by an error amplifier based on the regulated voltage and a reference voltage. The error amplifier may control a source-follower stage to mirror a multiple of the current flowing in the source-follower stage into an internal pass device. A voltage developed by the mirror current may control an external pass device configured to deliver the load current into the regulator output. A first resistor may be configured to decouple a load capacitor coupled between the regulator output and reference ground, when the load current is below a specified value. A second resistor may be configured to create a bias current in the internal pass device even when the external pass device is close to cut-off region. A third resistor may be configured to counter the effects of negative impedance at the control terminal of the external pass device caused by the current-gain of the external pass device. A compensation capacitor and resistor may be coupled in series between the output of the error amplifier and the output of the voltage regulator to provide frequency compensation for the Miller-Effect. | 08-26-2010 |
20110115423 | Brushless, Three Phase Motor Drive - A control method for a brushless, three-phase DC motor. A voltage induced by rotation of a rotor may be sampled at a first expected zero crossing value to produce a first sampled voltage value. An average of a plurality of sampled voltage values, including voltage values sampled at a plurality of prior expected zero crossing values and the first sampled voltage value, may be calculated. The first sampled voltage value may be subtracted from the calculated average to produce a delta zero crossing error. A pulse-width modulation duty cycle may be adjusted based on the delta zero crossing error. The pulse-width modulation duty cycle may be used to control a rotational velocity of the rotor. | 05-19-2011 |
20110128085 | Analog-to-Digital Converter in a Motor Control Device - System and method for digitizing analog voltage signals. A first voltage signal may be received at a comparator. A ramp signal may be received at the comparator. The ramp signal may be generated by a ramp generator. An output signal may be generated by the comparator. The output signal may indicate whether the analog voltage signal or the ramp signal is greater. The output signal may be conveyed to logic circuitry by the comparator. Control information may be conveyed by the logic circuitry to the ramp generator. The ramp generator may generate the ramp signal based on the control information. The logic circuitry may determine a digital representation of the first voltage signal based on the output signal from the comparator and the control information. | 06-02-2011 |
20110291625 | Low Power Regulator - A voltage regulator may derive current from a bias circuitry having a constant-transconductance. The bias circuitry may generate the bias current using three NMOS devices. The temperature coefficient of the bias current may be within a specified, desired range. The bias current may be mirrored to low-power regulator circuitry to bias a diode-connected transistor in the low-power regulator circuitry to operate in the strong inversion region. A ratioed current based on the output load current may be injected into a bipolar junction transistor (BJT) device to cause the gate-source voltage (V | 12-01-2011 |
20110291675 | Bi-Directional High Side Current Sense Measurement - A system for measuring a voltage drop between two nodes in an electrical circuit, comprising a switched capacitor integrator (SCI), a comparator and a counter. The SCI alternately (a) captures charge onto a set of sampling capacitors and (b) selectively accumulates/transfers the charge onto a pair of integration capacitors, where the charge includes a first portion that is based on the voltage drop and a second portion that depends on a digital indicator signal. The comparator generates the digital indicator signal based on whether an analog output of the SCI is positive or negative. The counter counts a number of ones occurring in the digital indicator signal during a measurement interval. At the end of the measurement interval, the count value represents a measure of the voltage drop. Knowing the resistance between the two nodes, the voltage drop may be converted into a current measurement. | 12-01-2011 |
20120092068 | Fringe Capacitor Using Bootstrapped Non-Metal Layer - A switched-capacitor circuit on a semiconductor device may include accurately matched, high-density metal-to-metal capacitors, using top-plate-to-bottom-plate fringe-capacitance for obtaining the desired capacitance values. A polysilicon plate may be inserted below the bottom metal layer, and bootstrapped to the top plate of each capacitor in order to minimize and/or eliminate the parasitic top-plate-to-substrate capacitance. This may free up the bottom metal layer to be used in forming additional fringe-capacitance, thereby increasing capacitance density. By forming each capacitance solely based on fringe-capacitance from the top plate to the bottom plate, no parallel-plate-capacitance is used, which may reduce capacitor mismatch. Parasitic bottom plate capacitance to the substrate may also be eliminated, with only a small capacitance to the bootstrapped polysilicon plate remaining. The capacitors may be bootstrapped by coupling the top plate of each capacitor to a respective one of the differential inputs of an amplifier comprised in the switched-capacitor circuit. | 04-19-2012 |
20120092069 | Circuit with High-Density Capacitors Using Bootstrapped Non-Metal Layer - A switched-capacitor circuit on a semiconductor device may include accurately matched, high-density metal-to-metal capacitors, using top-plate-to-bottom-plate fringe-capacitance for obtaining the desired capacitance values. A polysilicon plate may be inserted below the bottom metal layer, and bootstrapped to the top plate of each capacitor in order to minimize and/or eliminate the parasitic top-plate-to-substrate capacitance. This may free up the bottom metal layer to be used in forming additional fringe-capacitance, thereby increasing capacitance density. By forming each capacitance solely based on fringe-capacitance from the top plate to the bottom plate, no parallel-plate-capacitance is used, which may reduce capacitor mismatch. Parasitic bottom plate capacitance to the substrate may also be eliminated, with only a small capacitance to the bootstrapped polysilicon plate remaining The capacitors may be bootstrapped by coupling the top plate of each capacitor to a respective one of the differential inputs of an amplifier comprised in the switched-capacitor circuit. | 04-19-2012 |
20120094463 | High-Density Capacitor Configured On a Semiconductor - A switched-capacitor circuit on a semiconductor device may include accurately matched, high-density metal-to-metal capacitors, using top-plate-to-bottom-plate fringe-capacitance for obtaining the desired capacitance values. A polysilicon plate may be inserted below the bottom metal layer, and bootstrapped to the top plate of each capacitor in order to minimize and/or eliminate the parasitic top-plate-to-substrate capacitance. This may free up the bottom metal layer to be used in forming additional fringe-capacitance, thereby increasing capacitance density. By forming each capacitance solely based on fringe-capacitance from the top plate to the bottom plate, no parallel-plate-capacitance is used, which may reduce capacitor mismatch. Parasitic bottom plate capacitance to the substrate may also be eliminated, with only a small capacitance to the bootstrapped polysilicon plate remaining The capacitors may be bootstrapped by coupling the top plate of each capacitor to a respective one of the differential inputs of an amplifier comprised in the switched-capacitor circuit. | 04-19-2012 |