Patent application number | Description | Published |
20080250263 | Integrated Circuit Input/Output Interface with Empirically Determined Delay Matching - An integrated circuit input/output interface with empirically determined delay matching is disclosed. In one embodiment, the integrated circuit input/output interface uses empirical information of signal traces coupled to the integrated circuit to adjust a transmit/receive clock of each pin of the interface so as to compensate for delay mismatches caused by differences in signal trace lengths. In one embodiment, values representative of the empirical information are stored for use by the integrated circuit to generate trace-specific signals so as to compensate for delay differences that are at least partially caused by unmatched signal trace lengths. The empirical information, in one embodiment, includes signal flight time of each signal trace, which can be pre-measured or pre-calculated from known signal trace lengths. The empirical information, in another embodiment, includes trace-specific phase offset values calculated from pre-calculated or pre-measured signal flight times or signal trace lengths. | 10-09-2008 |
20090049324 | Methods and systems for operating memory in two modes - A memory system permits synchronized transmission of data with multiple memory modules in a dynamically expandable bus system such as with a point-to-point memory bus using strobed data transmission. Memory modules of the system are selectively configured to switch transmission modes to either transmit data to a memory controller or a timing reference signal to another memory module from a common terminal coupled to a common path of the bus which may depend on the number of memory modules configured in the system. The system permits all memory modules to operate with a strobed based memory controller even when some memory modules of the system do not share a strobe signal path with the memory controller of the system. | 02-19-2009 |
20090164677 | TIMING ADJUSTMENT IN A RECONFIGURABLE SYSTEM - This disclosure provides a method for adjusting system timing in a reconfigurable memory system. In a Dynamic Point-to-Point (“DPP”) system, for example, manufacturer-supplied system timing parameters such as access latency and maximum clock speed typically reflect a worst-case configuration scenario. By in-situ detecting actual configuration (e.g., whether expansion boards have been inserted), and correspondingly configuring the system to operate in a mode geared to the specific configuration, worst-case or near worst-case scenarios may be ruled out and system timing parameters may be redefined for faster-than-conventionally-rated performance; this is especially the case in a DPP system where signal pathways typically become more direct as additional modules are added. Contrary to convention wisdom therefore, which might dictate that component expansion should slow down timing, clock speed can actually be increased in such a system, if supported by the configuration, for better performance. | 06-25-2009 |
20090282189 | MEMORY CONTROLLER WITH REFRESH LOGIC TO ACCOMODATE LOW-RETENTION STORAGE ROWS IN A MEMORY DEVICE - A memory controller is disclosed that provides refresh control circuitry to generate first refresh commands directed to a first row of storage cells within a memory device at a first rate. The refresh control circuitry generates second refresh commands directed to a second row of storage cells within the memory device at a second rate. Output circuitry outputs the first and second refresh commands to the memory device. | 11-12-2009 |
20090300260 | SELECTIVE SWITCHING OF A MEMORY BUS - In a system, a memory bus has a first bus segment coupled to a memory controller that includes control logic and a first memory device, a second bus segment coupled to a second memory device, and a switch to selectively couple and decouple the first bus segment and the second bus segment in response to control information from the control logic. Note that the control logic may output control information to the switch to selectively decouple the first bus segment and the second bus segment to effect a change in an electrical length of the memory bus to enable data transfer with respect to the first memory device at a first data rate. Additionally, the control logic may output control information to the switch to selectively couple the first bus segment and the second bus segment to effect another change in the electrical length of the memory bus to enable data transfer with respect to the second memory device at a second data rate that is slower than the first data rate. | 12-03-2009 |
20100058100 | DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS - A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function. | 03-04-2010 |
20100073047 | Apparatus for Data Recovery in a Synchronous Chip-to-Chip System - An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device. | 03-25-2010 |
20100091537 | MULTI-DIE MEMORY DEVICE - An integrated circuit (IC) package includes an interface die and a separate storage die. The interface die has a synchronous interface to receive memory access commands from an external memory controller, and has a plurality of clockless memory control interfaces to output row and column control signals that correspond to the memory access commands. The storage die has a plurality of independently accessible storage arrays and corresponding access-control interfaces to receive the row and column control signals from the clockless memory control interfaces, each of the access-control interfaces including data output circuitry to output read data corresponding to a given one of the memory access commands in a time-multiplexed transmission. | 04-15-2010 |
20100110748 | HYBRID VOLATILE AND NON-VOLATILE MEMORY DEVICE - A composite, hybrid memory device including a first storage die having an array of volatile storage cells and a second storage die having an array of non-volatile storage cells disposed within an integrated circuit package. The hybrid memory device includes a shared interface circuit to receive memory access commands directed to the first storage die and the second storage die and to convey read and write data between an external data path and the first and second storage dice. | 05-06-2010 |
20100118627 | STROBE-OFFSET CONTROL CIRCUIT - A strobe offset control circuit is disclosed. The control circuit comprises a strobe signal input to receive a strobe signal and a data receiver to receive a data signal in response to a sample signal derived from the strobe signal. A calibration enable input is provided to receive a calibration enable signal. The calibration enable signal places the strobe offset control circuit in one of a calibration mode or a receiver mode. In the calibration mode, a phase offset between the data signal and the sample signal is adjusted based on output from the receiver. In the receiver mode, the phase offset between the data signal and the sample signal is not adjusted based on output from the receiver. | 05-13-2010 |
20100135370 | BI-DIRECTIONAL INTERFACE CIRCUIT HAVING A SWITCHABLE CURRENT-SOURCE BIAS - A bi-directional interface circuit includes a transmitter portion, a receiver portion, a current source bias circuit, and a switch. When the interface circuit is transmitting data, the switch steers the bias current generated by the current source bias circuit to the transmitter portion of the interface. When the interface is receiving data, the switch steers the bias current to the receiver portion of the interface. Thus, the current-source bias circuit is kept on regardless of whether the interface is transmitting or receiving data. Because the current-source bias circuit is not turned on and off, the switching noise generated when the interface transitions between transmitting and receiving operations is eliminated or reduced. Consequently, any dead time inserted for such a transition can be minimized, and the effective bandwidth of the interface is increased. | 06-03-2010 |
20100254204 | SELF-TIMED INTERFACE FOR STROBE-BASED SYSTEMS - A method is disclosed comprising detecting an edge-transition of a strobe signal using hysteresis, the strobe signal originating in a first clock domain. A count is controlled in a first direction in response to the detected edge-transition. The count is controlled in a second direction in response to an edge-transition of a clock signal, the clock signal originating in a second clock domain. Data is interfaced between the first and second clock domains in response to the count. | 10-07-2010 |
20110016278 | Independent Threading of Memory Devices Disposed on Memory Modules - A memory module includes a substrate having signal lines thereon that form a control path and a plurality of data paths. A plurality of memory devices are mounted on the substrate. Each memory device is coupled to the control path and to a distinct data path. The memory module includes control circuitry to enable each memory device to process a distinct respective memory access command in a succession of memory access commands and to output data on the distinct data path in response to the processed memory access command. | 01-20-2011 |
20110235727 | COMMUNICATION CHANNEL CALIBRATION WITH NONVOLATILE PARAMETER STORE FOR RECOVERY - A communication channel is operated by storing a calibrated parameter value in nonvolatile memory during manufacturing, testing, or during a first operation of the device. Upon starting operation of the communication channel in the field, the calibrated parameter value is obtained from the nonvolatile memory, and used in applying an operating parameter of the communication channel. After applying the operating parameter, communication is initiated on a communication channel. The operating parameter can be adjusted to account for drift immediately after starting up, or periodically. The process of starting operation in the field includes power up events after a power management operation. In embodiments where one component includes memory, steps can be taken prior to a power management operation using the communication channel, such as transferring calibration patterns to be used in calibration procedures. | 09-29-2011 |
20110255615 | Apparatus for Data Recovery in a Synchronous Chip-to-Chip System - An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device. | 10-20-2011 |
20120033514 | STROBE-OFFSET CONTROL CIRCUIT - A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A first sample signal is generated based on the first phase relationship and a second sample signal is generated based on the second phase relationship. The first data signal is received using a first receiver clocked by the first sample signal. The second data signal is received using a second receiver clocked by the second sample signal. | 02-09-2012 |
20120068360 | Stacked Semiconductor Device Assembly - The semiconductor device system includes multiple stacked substantially identical semiconductor devices each including a first side and an opposing second side. First and second pads are disposed at the first side of the semiconductor device, while third and fourth pads are disposed at the second side of the semiconductor device. First interface circuit is electrically coupled to the first pad and the third pad, while second interface circuit is electrically coupled to the second pad and the fourth pad. The second interface circuit is separate and distinct from the first interface circuit. At least one first semiconductor device of the multiple semiconductor devices is offset from other of the multiple semiconductor devices such that the fourth pad on the first semiconductor device is aligned with, and electrically connected to, the first pad on an adjacent one of the multiple semiconductor devices. In some embodiments, the first pad is associated with a first capacitance, while the second pad is associated with a second capacitance that is smaller than the first capacitance. | 03-22-2012 |
20120110229 | SELECTIVE SWITCHING OF A MEMORY BUS - A memory bus with a first bus segment coupled to a memory controller that includes control logic and a first memory device, a second bus segment coupled to a second memory device, and a switch between the first bus segment and the second bus segment. The control logic outputs control information to the switch to selectively decouple the first bus segment and the second bus segment to effect a change in the length of the memory bus to enable data transfer with respect to the first memory device at a first data rate. Additionally, the control logic may output control information to the switch to selectively couple the first bus segment and the second bus segment to increase the length of the memory bus to enable data transfer with respect to the second memory device at a second data rate that is slower than the first data rate. | 05-03-2012 |
20120147979 | Forwarding Signal Supply Voltage in Data Transmission System - In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit. | 06-14-2012 |
20120166863 | Methods And Apparatus For Synchronizing Communication With A Memory Controller - A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals. | 06-28-2012 |
20120182776 | DRAM DEVICE WITH BUILT-IN SELF-TEST CIRCUITRY - A dynamic random access memory (DRAM) device includes a first and second integrated circuit (IC) die. The first integrated circuit die has test circuitry to generate redundancy information. The second integrated circuit die is coupled to the first integrated circuit die in a packaged configuration including primary storage cells and redundant storage cells. The second integrated circuit die further includes redundancy circuitry responsive to the redundancy information to substitute one or more of the primary storage cells with one or more redundant storage cells. | 07-19-2012 |
20120294058 | MULTI-DIE MEMORY DEVICE - A multi-die memory device includes a first die of a first type and configured to electrically interface with an external processor via a first synchronous interface operating at a first clock rate, and at least one second die of a second type and configured for data storage. Each second die transacts data with the first die via a second synchronous interface operating at a second clock rate, where the first clock rate is an integer multiple of the second clock rate, and where a timing reference associated with the second synchronous interface is transmitted by the first die to the second die. | 11-22-2012 |
20120311251 | Coordinating Memory Operations Using Memory-Device Generated Reference Signals - A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal. | 12-06-2012 |
20120327726 | Methods and Circuits for Dynamically Scaling DRAM Power and Performance - A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface. The memory core employs core supply voltages that remain the same in both modes. Supply voltages and signaling rates for the core interface may be scaled down to save power. Level shifters between the memory core and core interface level shift signals as needed to accommodate the signaling voltages used by the core interface in the different modes. | 12-27-2012 |
20130044552 | STROBE-OFFSET CONTROL CIRCUIT - A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A first sample signal is generated based on the first phase relationship and a second sample signal is generated based on the second phase relationship. The first data signal is received using a first receiver clocked by the first sample signal. The second data signal is received using a second receiver clocked by the second sample signal. | 02-21-2013 |
20130057318 | CLOCKING ARCHITECTURES IN HIGH-SPEED SIGNALING SYSTEMS - Clocking systems and methods are provided below that accurately clock per-pin data transfers of input/output (IO) circuits of integrated circuit devices. These multiplexer-based clock selection systems use a dedicated multiplexer to receive clock signals from multiple mixer circuits and in turn to provide a selected reference clock signal for use by an interface circuit in transferring data to other integrated circuit devices. The timing of the selected reference clock signal is synchronized with the data signals to provide optimal sampling of the data signals. The multiplexer-based clock selection system is for use in memory interfaces of high-speed signaling systems for example. | 03-07-2013 |
20130094310 | METHODS AND APPARATUS FOR SYNCHRONIZING COMMUNICATION WITH A MEMORY CONTROLLER - A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals. | 04-18-2013 |
20130208818 | MEMORY COMPONENTS AND CONTROLLERS THAT UTILIZE MULTIPHASE SYNCHRONOUS TIMING REFERENCES - Multiple timing reference signals (e.g., clock signals) each cycling at the same frequency are distributed in a fly-by topology to a plurality of memory devices in various embodiments are presented. These multiple clock signals each have a different phase relationship to each other (e.g., quadrature). A first circuit receives a first of these clocks as a first timing reference signal. A second circuit receives a second of these clocks as a second timing reference signal. A plurality of receiver circuits receive signals synchronously with respect to the first timing reference signal and the second timing reference signal, such that a first signal value is resolved using the first timing reference signal and a second signal value is resolved using the second timing reference signal. | 08-15-2013 |
20130308383 | HYBRID VOLATILE AND NON-VOLATILE MEMORY DEVICE - A composite, hybrid memory device including a first storage die having an array of volatile storage cells and a second storage die having an array of non-volatile storage cells disposed within an integrated circuit package. The hybrid memory device includes a shared interface circuit to receive memory access commands directed to the first storage die and the second storage die and to convey read and write data between an external data path and the first and second storage dice. | 11-21-2013 |
20140068169 | Independent Threading Of Memory Devices Disposed On Memory Modules - A memory module includes a substrate having signal lines thereon that form a control path and a plurality of data paths. A plurality of memory devices are mounted on the substrate. Each memory device is coupled to the control path and to a distinct data path. The memory module includes control circuitry to enable each memory device to process a distinct respective memory access command in a succession of memory access commands and to output data on the distinct data path in response to the processed memory access command. | 03-06-2014 |
20140153310 | CONTENT ADDRESSABLE MEMORY - A content addressable memory can include an array of memory cells having multiple memory elements, such as RRAM elements, to store data based on a plurality resistive states. A common switching device, such as a transistor, can electrically couple a plurality of the multiple memory elements with a matchline during read, write, erase, and search operations. In search operations, the memory cells can receive a search word and selectively discharge a voltage level on the matchline based on the data stored by the memory elements and the search word provided to the memory elements. The voltage level of the matchline can indicate whether the search word matched the data stored in the memory cells. The content addressable memory can potentially have an effective memory cell sizing under 0.5F | 06-05-2014 |
20140185725 | DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS - A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function. | 07-03-2014 |
20140233333 | METHODS AND APPARATUS FOR SYNCHRONIZING COMMUNICATION WITH A MEMORY CONTROLLER - A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals. | 08-21-2014 |
20140247637 | MULTI-DIE MEMORY DEVICE - A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays. | 09-04-2014 |
20140293725 | MEMORY WITH REFRESH LOGIC TO ACCOMODATE LOW-RETENTION STORAGE ROWS - An apparatus is disclosed that includes a memory controller chip and memory chips packaged with the memory controller chip. Each memory chip includes normal-retention storage rows that exhibit retention times greater or equal to a first time interval, and having been tested to generate information identifying low-retention storage rows that exhibit retention times less than the first time interval. Refresh logic refreshes the normal-retention storage rows at a first refresh rate corresponding to the first time interval, and refreshes each low-retention storage row at a second refresh rate that is greater than the first refresh rate. | 10-02-2014 |
20140351500 | HYBRID VOLATILE AND NON-VOLATILE MEMORY DEVICE - Non-transitory computer-readable media having information embodied therein that includes a description of an integrated circuit device. The information includes descriptions of a volatile storage die having a first addressable range of storage cells and a non-volatile storage die. The description of the non-volatile storage die having a second addressable range of storage cells that defines an overlapping region with the first addressable range of storage cells. The information also includes a description of an interface circuit coupled to the volatile and non-volatile storage die to selectively transfer data stored in the overlapping region of storage cells between the die. | 11-27-2014 |
20140351673 | DRAM METHOD, COMPONENTS, AND SYSTEM CONFIGURATIONS FOR ERROR MANAGEMENT - A memory device is disclosed that includes a row of storage locations to store a data word, and a spare row element. The data word is encoded via an error code for generating error information for correcting X bit errors or detecting Y bit errors, where Y is greater than X. The spare row element has substitute storage locations. The logic is responsive to detected errors to (1) enable correction of a data word based on the error information where there are no more than X bit errors, and (2) substitute the spare row element for a portion of the row where there are at least Y bit errors in the data word. | 11-27-2014 |
20150033044 | Methods and Circuits for Dynamically Scaling DRAM Power and Performance - A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface. The memory core employs core supply voltages that remain the same in both modes. Supply voltages and signaling rates for the core interface may be scaled down to save power. Level shifters between the memory core and core interface level shift signals as needed to accommodate the signaling voltages used by the core interface in the different modes. | 01-29-2015 |
20150082119 | Memory Module with Integrated Error Correction - A memory system includes a memory module that supports error detection and correction (EDC) in a manner that relieves a memory controller or processor of some or all of the computational burden associated with EDC. individual EDC components perform EDC functions on subsets of the data, and share data between themselves using relatively short, fast interconnections. | 03-19-2015 |