Patent application number | Description | Published |
20130205072 | ASYNCHRONOUS BAD BLOCK MANAGEMENT IN NAND FLASH MEMORY - Methods for receiving data from a file system and storing it in a flash storage medium, wherein a bad block management process comprises queuing, at a bad block manager, one or more write requests, and receiving data associated with each of the one or more write requests and storing the received data in the bad block manager buffer; and performing cache management of data in the bad block manager buffer and subsequently returning a success status to the file system; and executing the one or more queued write requests in a separate task, wherein the executing comprises programming the received data to the flash storage medium during the bad block management process. Corresponding devices are also provided. | 08-08-2013 |
20130254511 | Improving Storage Lifetime Using Data Swapping - A memory management system for managing memory of a processing system having a primary memory and at least one secondary memory is disclosed. The memory is managed by optimizing the number of writes required by swapping one or more relevant pages of an application from the primary memory to the at least one secondary memory. The system comprises of a dynamic memory manager for allocating memory to the application from a memory pool and having a first table containing virtual addresses and chunk sizes of memory allocated by the application. The system further comprises of a swap manager having a second table containing the physical addresses of the primary memory pages and information whether the pages are allocated or not. The system further comprises of a memory management unit having a third table containing a mapping information of the physical addresses and the virtual addresses of the one or more physical pages used by the application and information whether the page is dirty or not. | 09-26-2013 |
20130326170 | Methods and Devices for Reducing Compressed Page Loading Time on Page Fault - Exemplary embodiments provide for compressing, storing, retrieving and decompressing paged code from mass storage devices. By evaluating the size of compressed virtual pages relative to the storage page (read unit) of the mass storage device into which the compressed virtual pages are to be stored, decisions can be made which facilitate later read out and decompression of those compressed virtual pages. According to exemplary embodiments, a virtual page can be stored uncompressed, compressed but undivided or compressed and subdivided into a plurality of parts based on an evaluation. | 12-05-2013 |
20140025906 | Device Controller for a Memory Device - The invention provides a method for controlling writing of data to a data storage card having a device controller and a storage medium. Particularly, the device controller receives a meta data synchronization disable command and in response, enters a first mode. In the first mode, the device controller does not synchronize meta data related to a data write request to write the data to the storage medium, leaving corresponding unsynchronized meta data. The device controller receives a data write request to write the data, and in response, effects the data write request such that the data is written to the storage medium. However, the meta data related to the data write request is not synchronized to the storage medium. Other aspects provide a corresponding device controller and software/firmware. | 01-23-2014 |
20150074355 | EFFICIENT CACHING OF FILE SYSTEM JOURNALS - An apparatus includes a memory and a controller. The memory may be configured to implement a cache and store meta-data. The cache generally comprises one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. Each of the plurality of cache-lines is associated with meta-data indicating one or more of a dirty state, an invalid state, and a partially dirty state. The controller is connected to the memory and may be configured to (i) detect an input/output (I/O) operation directed to a file system recovery log area, (ii) mark a corresponding I/O using a predefined hint value, and (iii) pass the corresponding I/O along with the predefined hint value to a caching layer. | 03-12-2015 |
20150178201 | SYSTEM FOR EFFICIENT CACHING OF SWAP I/O AND/OR SIMILAR I/O PATTERN(S) - An apparatus comprising a memory and a controller. The memory may be configured to (i) implement a cache and (ii) store meta-data. The cache may comprise one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. The controller is connected to the memory and configured to (A) process normal read/write operations in a first mode and (B) process special read/write operations in a second mode by (i) tracking a write followed by read condition on each of said cache windows and (ii) discarding data on the cache-lines associated with the cache windows after completion of the write followed by a read condition on the cache-lines. | 06-25-2015 |
20150199269 | ENHANCED SSD CACHING - An apparatus comprising a memory and a controller. The memory may be configured to (i) implement a cache and (ii) store meta-data. The cache comprises one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. Each of the plurality of cache-lines may be associated with meta-data indicating one or more of a dirty state and an invalid state. The controller may be connected to the memory and configured to detect an input/output (I/O) operation directed to a file system. The controller may perform a read-fill based on a hint value when there is a read miss in the cache. The hint value may be based on the application access pattern. The hint value may be passed to a caching layer with a corresponding I/O. | 07-16-2015 |
20150220452 | System, Method and Computer-Readable Medium for Dynamically Mapping a Non-Volatile Memory Store - Applications that use non-volatile random access memory (NVRAM), such as those that apply file system journal writes and database log writes where write operations apply data sequentially over the NVRAM, map the available capacity of the NVRAM in a virtual address space without compromising performance. The NVRAM is segmented into regions with multiple such regions fitting within a volatile RAM element accessible to the application and the NVRAM. One or more regions are loaded in the volatile RAM and reflected in page tables that reference the regions. The page tables are managed on a host computer executing the application. One region space in the volatile RAM is unused and available for transferred information. Mechanisms are provided for dynamically transferring regions and interfacing with the host computer. As the application sequentially accesses information in the stored regions, older regions are removed and new regions loaded from NVRAM to the volatile RAM. | 08-06-2015 |