Patent application number | Description | Published |
20120038809 | DIFFERENTIAL COLUMN ADC ARCHITECTURES FOR CMOS IMAGE SENSOR APPLICATIONS - Circuits, methods, and apparatus that provide differential-input, single-slope, column-parallel analog-to-digital converter (ADC) architectures for use in high-resolution CMOS image sensors (CIS) are described. A column ADC is coupled with a column of a pixel array and configured to convert a pixel signal level to a corresponding digital output value according to a ramp generator output. Each pixel is configured to output a pixel reset level and a pixel signal level at different operating stages, and the ramp generator output includes a ramp reset level and a ramp signal level at the same or different at different operating stages. The pixel and ramp outputs are used to differentially drive a comparator stage of the column ADC, for example, to reduce power supply noise. | 02-16-2012 |
20120039548 | FRAME-WISE CALIBRATION OF COLUMN-PARALLEL ADCS FOR IMAGE SENSOR ARRAY APPLICATIONS - Circuits, methods, and apparatus are described that provide calibration of column-parallel analog-to-digital converters (ADCs) in image processing contexts only once per frame (or less frequently) to reduce column-wise noise. For example, the column ADCs are calibrated during an inter-frame time interval, like a vertical blanking interval. In some embodiments, calibration data for the column ADCs for a calibration period is stored at the digital block for use in processing row data from the column ADCs. In other embodiments, calibration data for the column ADCs for the calibration period is stored at column ADCs in a local memory for local correction of the pixel data prior to being read out to the digital block for processing. In certain embodiments, techniques, such as differential ADC architectures, are used to mitigate row-wise noise in context of the frame-wise calibration. | 02-16-2012 |
20120169909 | IMAGE PROCESSING SYSTEM WITH ON-CHIP TEST MODE FOR COLUMN ADCS - An image processing system includes a pixel array including a plurality of regular pixel columns and at least one test pixel column, a plurality of column analog-to-digital converters (ADCs) configured to correspond to the regular pixel columns and convert analog input signals into digital signals, and a switching block configured to provide output signals of the regular pixel columns to input ends of the corresponding column ADCs in a normal mode, and provide in common an output signal of the test pixel column to the input ends of the column ADCs in a test mode, wherein the test pixel column generates signals having a minute voltage different from one row to another row. | 07-05-2012 |
20120194252 | METHOD OF SHIFTING AUTO-ZERO VOLTAGE IN ANALOG COMPARATORS - Aspects of the invention provide, inter alia, techniques for shifting auto-zero voltage in analog comparators. An embodiment of the invention may include at least one diode configured transistor to increase a drain voltage of at least one NMOS load transistor. A first switch and a second switch may be implemented to increase a voltage at a gate of a first PMOS input transistor and a voltage at a gate of a second PMOS input transistor when the first switch and the second switch are closed. | 08-02-2012 |
20120194261 | CASCODED COMPARATOR WITH DYNAMIC BIASING FOR COLUMN PARALLEL SINGLE SLOPE ADCS - Aspects of the invention may include receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively. | 08-02-2012 |
20120194368 | METHOD AND SYSTEM FOR CALIBRATING COLUMN PARALLEL ADCS - Various embodiments of the invention include enabling, during a calibration phase, a counter to count one less than a number of clock periods associated with a determined offset. The counted number of the clock periods is stored in calibration memory. In a conversion phase, inverted outputs are loaded from the calibration memory to the counter, where the counter is enabled to count the clock periods to determine a digital equivalent value of an analog signal amplitude. | 08-02-2012 |
20120306674 | AUTOMATIC OFFSET ADJUSTMENT FOR DIGITAL CALIBRATION OF COLUMN PARALLEL SINGLE-SLOPE ADCS FOR IMAGE SENSORS - Various embodiments of the present invention include enabling, during a calibration phase, a counter to count one less than a number of clock periods associated with a determined offset. The counted number of the clock periods is stored in calibration memory. In a conversion phase, inverted outputs are loaded from the calibration memory to the counter, where the counter is enabled to count the clock periods to determine a digital equivalent value of an analog signal amplitude. | 12-06-2012 |
20150097596 | CASCODED COMPARATOR WITH DYNAMIC BIASING FOR COLUMN PARALLEL SINGLE SLOPE ADCS - Aspects of the invention may comprise receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, that tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively. | 04-09-2015 |