Patent application number | Description | Published |
20120306550 | SEMICONDUCTOR APPARATUS AND METHOD FOR CONTROLLING THE SAME - A semiconductor apparatus comprises a power-up signal generation section configured to generate a power-up signal, a driver configured to drive and output the power-up signal, and a main circuit block configured to perform predetermined functions in response to an output from the driver, wherein the power-up signal generation section and an input terminal of the driver are connected by a disconnectable element. | 12-06-2012 |
20130051165 | SEMICONDUCTOR APPARATUS AND DATA TRANSMISSION METHOD THEREOF - A semiconductor apparatus includes a normal data line, an auxiliary data line and a data line selection unit. The normal data line is connected with a data selection unit. The auxiliary data line is connected with the data selection unit. The data line selection unit outputs data to one of the normal data line and the auxiliary data line in response to a command signal. | 02-28-2013 |
20140167281 | STACK TYPE SEMICONDUCTOR CIRCUIT WITH IMPEDANCE CALIBRATION - A stack type semiconductor circuit includes a plurality of semiconductor chips stacked therein, wherein the plurality of semiconductor chips are configured to share impedance calibration information. The plurality of semiconductor chips include at least one resistance value of an external resistor and an impedance calibration signal as the impedance calibration information. | 06-19-2014 |
20140175668 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a first interface block configured to transmit and receive signals within the same chip; a second interface block configured to transmit and receive signals to and from different semiconductor chips; and a switching block configured to select a signal path in which the signal transmission and reception of the first interface block is not performed through the second interface block, in response to a chip structure signal. | 06-26-2014 |
20140344613 | SEMICONDUCTOR APPARATUS AND MEMORY SYSTEM - A semiconductor apparatus includes a chip ID generation unit, a chip ID transmission unit and a chip stack information generation unit. The chip ID generation unit is configured to generate a chip ID signal. The chip ID transmission unit is configured to output the chip ID signal to a common line on the basis of whether another chip is electrically coupled therewith. The chip stack information generation unit is configured to be electrically coupled with the common line in response to the chip ID signal and generate a stack information signal. | 11-20-2014 |
20150155857 | FLIP-FLOP CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME - A flip-flop circuit may include: a latch unit configured to latch an input signal in response to a clock signal; and a timing control unit configured to delay a signal provided from the latch unit by a predetermined time regardless of the clock signal. | 06-04-2015 |
20150162911 | OPERATION MODE SETTING CIRCUIT OF SEMICONDUCTOR APPARATUS AND DATA PROCESSING SYSTEM USING THE SAME - An operation mode setting circuit of a semiconductor apparatus includes a mode register set configured to update an operation mode information generated internally at the semiconductor apparatus based on preliminary information data in response to a preliminary information setting signal and a preliminary information providing block configured to provide the preliminary information data selected from a plurality of pre-stored preliminary information data to the mode register setting response to the preliminary information setting signal, the selected preliminary information data corresponding to a detected operation parameter detected in response to the preliminary information setting signal. | 06-11-2015 |
20150187405 | STACKED SEMICONDUCTOR APPARATUS FOR GENERATING REFRESH SIGNAL - A stacked semiconductor apparatus includes a plurality of chips which are stacked one upon the other. One chip of the plurality of chips may be configured to generate a plurality of refresh period signals for performing refresh operations within the plurality of chips, and may be configured to transmit the plurality of refresh period signals to the plurality of chips excluding the one chip. The plurality of chips may respectively receive refresh period signals allocated to them according to chip ID signals, and may perform the refresh operations. | 07-02-2015 |
20150188542 | DATA TRANSMISSION CIRCUIT - A data transmission circuit may include a first driving block configured to drive an output terminal for a first time in response to a data driving signal and a level of the output terminal, and a second driving block configured to drive the output terminal for a second time after the first time, in response to the data driving signal. | 07-02-2015 |