Patent application number | Description | Published |
20090249149 | LOW OVERHEAD SOFT ERROR TOLERANT FLIP FLOP - A system and method for soft error recovery (SER) within a flip-flop. A first stage of the flip-flop receives an ungated input clock signal. A second stage of the flip-flop receives a gated input clock signal. The second stage may also store a prebuffered data output and one or more feedback storage values on separate nodes. The flip-flop has SER circuitry used to recover the prebuffered data output and any feedback storage value without requiring a transition of a clock signal. | 10-01-2009 |
20090256593 | PROGRAMMABLE SAMPLE CLOCK FOR EMPIRICAL SETUP TIME SELECTION - A system and method for efficient improvement of timing analysis for faster processor designs with negligible impact on die-area. Rather than provide a single clock to flip-flop circuits on a semiconductor chip, split clocks are used. A flip-flop receives a master clock signal for a master latch and receives a separate slave clock signal for a slave latch. Master and slave clock gater circuits are coupled to a global clock distribution system and the local flip-flops. The master clock gater circuit receives a delay control signal used to select a delay, wherein the selected delay determines an additional amount of time the master clock signal transitions after the slave clock signal transitions. The use of the delayed master clock on the semiconductor chip may allow a timing path to have more computation time without increasing the clock cycle time. Further, the delay may be chosen to fix timing paths in post-silicon. | 10-15-2009 |
20090256609 | LOW POWER FLIP FLOP THROUGH PARTIALLY GATED SLAVE CLOCK - A system and method for reducing power consumption within a flip-flop circuit on a semiconductor chip. A gated input clock signal is received by a slave latch. The gated input clock is derived from an ungated input clock signal and a clock gating condition. The clock gating condition determines when an input data signal of the flip-flop and the stored internal state of the slave latch have the same logic value, such as only a logic low value. If they have the same value, toggling of the ungated input clock signal is not received by the slave latch, signal switching of internal nodes of the slave latch is reduced, and power consumption is reduced. | 10-15-2009 |
20090259869 | SAMPLING CHIP ACTIVITY FOR REAL TIME POWER ESTIMATION - A system and method for real-time power estimation. A core may be divided into units. Each unit is simulated to achieve a real power consumption characterization. The power consumption is sampled. Statistical analysis is performed that assumes the core has node capacitance switching behavior that is approximated by a stationary random process with a Poisson distribution. The statistical analysis determines the number of samples to take during a sample interval. The operational frequency, sample interval, and number of samples are used to determine the number of signals to sample. Signals are chosen that have a high correlation with the node capacitance switching behavior, such as clock enable signals on the last stage of a clock distribution system. Weights with tuned values are assigned to each sampled signal. Sampling occurs during every predetermined number of clock cycles. The weights of asserted sampled signals are summed in order to determine a repeatable power estimation value. | 10-15-2009 |
20090300329 | VOLTAGE DROOP MITIGATION THROUGH INSTRUCTION ISSUE THROTTLING - A system and method for providing a digital real-time voltage droop detection and subsequent voltage droop reduction. A scheduler within a reservation station may store a weight value for each instruction corresponding to node capacitance switching activity for the instruction derived from pre-silicon power modeling analysis. For instructions picked with available source data, the corresponding weight values are summed together to produce a local current consumption value and this value is summed with any existing global current consumption values from corresponding schedulers of other processor cores yielding an activity event. The activity event is stored. Hashing functions within the scheduler are used to determine both a recent and an old activity average using the calculated activity event and stored older activity events. Instruction issue throttling occurs if either a difference between the old activity average and the recent activity average exceed a first threshold or the recent activity average exceeds a second threshold. | 12-03-2009 |
20100072961 | INTERPOSER INCLUDING VOLTAGE REGULATOR AND METHOD THEREFOR - A device that includes an electronic device referred to as an integrated circuit interposer is disclosed. The integrated circuit includes a voltage regulator module. The interposer is attached to an electronic device, such as another integrated circuit, and facilitates control and distribution of power to the electronic device. The integrated circuit interposer can also conduct signaling between the attached electronic device and another electronic device. The voltage regulator module at the integrated circuit interposer can be configured to provide a voltage reference signal to the attached electronic device. Generation of the voltage reference signal by the integrated circuit interposer can be enabled or disabled and the value of the voltage reference signal can be adjusted, depending on operating requirements of the electronic device. | 03-25-2010 |
20100122101 | METHOD AND APPARATUS FOR REGULATING POWER CONSUMPTION - A method for controlling power consumption while maximizing processor performance. The method includes, for a time interval of operation in a first operational state, determining an amount of power consumed during by one or more cores of a processor, calculating, a power error based on the amount of power consumed in the time interval, obtaining a power error term for the interval by adding the power error to a power error term from a previous time interval, and comparing the power error term to at least a first error threshold. If the power error term is outside a range defined at least in part by the first error threshold, the method exits the first operational state and enters a second operational state. If the power error term is within the range defined at least in part by the first error threshold, operation continues in the first operational state. | 05-13-2010 |
20110301889 | FLEXIBLE POWER REPORTING IN A COMPUTING SYSTEM - A system and method for efficient reporting of power usage. A power reporting unit within a processor receives a power consumption number once every sample interval from a power monitor. The power monitor determines a power consumption number based on data corresponding to activity levels of one or more functional blocks within the processor. This data corresponds to each of a number of sampled signals within the one or more functional blocks rather than temperature. Thus, the data is independent of environment temperature variations. An average power consumption number is computed based on received power consumption numbers for a running time interval, wherein the running time interval is larger than the sample interval. This value is conveyed to an external agent, such as a controller for a data center rack system. Responsive to receiving and processing the average power consumption number, the external agent may perform one or more actions. For example, the external agent may cause changes in a cooling system. | 12-08-2011 |
20110314312 | MANAGING MULTIPLE OPERATING POINTS FOR STABLE VIRTUAL FREQUENCIES - A system and method for managing multiple discrete operating points to create a stable virtual operating point. One or more functional blocks within a processor produces data corresponding to an activity level associated with the respective functional block. A power manager determines a power consumption value based on the data once every given sample interval. In addition, the power manager determines a signed accumulated difference over time between a thermal design power (TDP) and the power consumption value. The power manager selects a next power-performance state (P-state) based on comparisons of the signed accumulated difference and given thresholds. Transitioning between P-states in this manner while the workload does not significantly change causes the processor to operate at a virtual operating point between supported discrete operating points. | 12-22-2011 |
20120023345 | MANAGING CURRENT AND POWER IN A COMPUTING SYSTEM - A system and method for efficient power transfer on a die. A semiconductor chip comprises on a die two or more computation units (CUs) utilizing at least two different voltage regulators and a power manager. The power manager reallocates power credits across the die when it detects an activity level of a given CU is below a given threshold. In response to receiving a corresponding number of donated power credits, each of the one or more selected CUs maintains a high activity level with a high performance P-state. When a corresponding workload increases, each CU maintains operation and an average power consumption corresponding to the high performance P-state by alternating between at least two different operational voltages. When the operational voltage drops during the alternation, the current drawn by the particular CU may exceed a given current limit. The power manager detects this current limit is exceeded and accordingly reallocates the power credits across the die. | 01-26-2012 |
20120066535 | MECHANISM FOR CONTROLLING POWER CONSUMPTION IN A PROCESSING NODE - A system includes a plurality of processor cores and a power management unit. The power management unit may be configured to independently control the performance of the processor cores by selecting a respective thermal power limit for each of the plurality of processor cores dependent upon an operating state of each of the processor cores and a relative physical proximity of each processor core to each other processor core. In response to the power management unit detecting that a given processor core is operating above the respective thermal power limit, the power management unit may reduce the performance of the given processor core, and thereby reduce the power consumed by that core. | 03-15-2012 |
20120105050 | METHOD AND SYSTEM FOR VARYING SAMPLING FREQUENCY TO AVOID SOFTWARE HARMONICS WHEN SAMPLING DIGITAL POWER INDICATORS - A method and system for varying sampling frequency to avoid software harmonics when sampling digital power indicators are described herein. A power monitor may repetitively sample, at a variable sampling rate based on a variable delay time, multiple signals of an IC device to obtain energy values. The variable delay time may be based on a pseudo-random value or a predictable value. The variable delay time may indicate a number of delay cycles that may be inserted between the repetitive samples of the energy values. The variable number of delay cycles between energy value samples may produce a variable sampling rate. A variable sampling rate may avoid alignment with software harmonics which can cause an inaccurate representation of power consumption. The multiple samples obtained by repetitively sampling energy value for the portion of the IC may be summed to generate a cumulative energy value for the portion of the IC. | 05-03-2012 |
20120105129 | APPARATUS FOR MONOLITHIC POWER GATING ON AN INTEGRATED CIRCUIT - A power gating apparatus includes an integrated circuit package with a first voltage reference plane and a second voltage reference plane, and an integrated circuit that includes a circuit block, and a switch block. The first and second voltage reference planes may be electrically isolated from one another. The switch block may include a plurality of switches arranged in a ring surrounding the circuit block. The first voltage reference plane may be electrically coupled between an external voltage reference and the plurality of switches, and the second voltage reference plane may be electrically coupled between the plurality of switches and the circuit block. The second voltage reference plane may also distribute an electric current throughout the circuit block. In addition, each of the switches is configured to interrupt an electrical path between the first reference voltage plane and the circuit block in response to a control signal. | 05-03-2012 |
20120109550 | METHOD AND SYSTEM OF SAMPLING TO AUTOMATICALLY SCALE DIGITAL POWER ESTIMATES WITH FREQUENCY - A method for automatically scaling estimates of digital power consumed by a portion of an integrated circuit (IC) device by the operating frequency of the portion of the IC are described herein. The method may include obtaining an energy value which may correspond to an amount of energy used by the portion of the IC. A cumulative energy value may be generated by repeatedly, at a frequency proportional to the operating frequency of the portion of the IC, obtaining energy values and adding each obtained energy value to a sum of energy values for the portion of the IC. The cumulative energy value may be sampled at a time sample interval to generate an estimate of the portion of the IC's digital power consumption that is automatically scaled with the operating frequency of the portion of the IC. | 05-03-2012 |
20120110352 | METHOD AND APPARATUS FOR THERMAL CONTROL OF PROCESSING NODES - An apparatus and method for per-node thermal control of processing nodes is disclosed. The apparatus includes a plurality of processing nodes, and further includes a power management unit configured to set a first frequency limit for at least one of the plurality of processing nodes responsive to receiving an indication of a first detected temperature greater than a first temperature threshold, wherein the first detected temperature is associated with the one of the plurality of processing nodes. The power management unit is further configured to set a second frequency limit for each of the plurality of processing nodes responsive to receiving an indication of a second temperature greater than a second temperature threshold. | 05-03-2012 |
20120144215 | MAXIMUM CURRENT LIMITING METHOD AND APPARATUS - The maximum current is limited in a multi-processor core system by monitoring the latest power consumption in the processor cores, in order to prevent a system shutdown as a result of an over-current event. If the sum of the latest power of the processor cores exceeds a threshold limit, a performance state (P-state) limit is enforced in the processor cores. The P-state limit causes a P-state change to a lower frequency, voltage and thus a lower current. | 06-07-2012 |
20120144221 | LOAD STEP MITIGATION METHOD AND APPARATUS - A method and apparatus for load step, or instantaneous current spike, mitigation are provided. In the method and apparatus, load steps are mitigated if a computer system a whole is lightly load, which may be determined by the power consumption of the computer system. Further, load steps are mitigated if a number of processor cores capable of inducing a load step is higher than a threshold. The Advanced Configuration and Power Interface (ACPI) performance state of the cores is used to determine a core's potential for generating a load step. A processor core is instructed to mitigate load steps if conditions are met for the mitigation. | 06-07-2012 |
20120146708 | METHOD AND APPARATUS FOR APPLICATION OF POWER DENSITY MULTIPLIERS OPTIMALLY IN A MULTICORE SYSTEM - A method and an apparatus are described that delay application of a higher order Power Density Multiplier (PDM) using a time based moving average of a number of active cores in a multicore system. A PDM is applied to a thermal design power budget of a thermal entity and performance of the thermal entity is increased by transferring available power from a thermal entity not in an active state to a thermal entity in an active state. Sufficient time is allowed for the cooling effect of reduced active cores, to influence the active core that receives the extra power (a higher PDM). Similarly delaying application of a lower PDM with the same moving average, but a different threshold, allows a core to retain a higher power allocation until the more active neighbor core(s) cause it to heat up, thereby boosting core performance. | 06-14-2012 |
20120154188 | SENSE-AMPLIFIER MONOTIZER - A sense-amplifier monotizer includes an amplifier circuit and a keeper circuit. The amplifier circuit outputs a predetermined logic state while a clock signal is in a first phase, and samples a data signal and outputs at least one of the data signal and a complementary logic state of the data signal while the clock signal is in a second phase. A subsequent change of the data signal does not affect an output of the amplifier circuit once the data signal is sampled while the clock signal is in the second phase. The keeper circuit keeps a logic state of the sampled data signal once the data signal is sampled while the clock signal is in the second phase. The amplifier circuit may receive multiple data signals, and output a data signal selected by the select signal and/or a complementary value while the clock signal is in the second phase. | 06-21-2012 |
20120159123 | CSTATE BOOST METHOD AND APPARATUS - A central processing unit (processor) having multiple cores and a method for controlling the performance of the processor. The processor includes a first storage location configured to store a first threshold associated with a first boost performance state (P-State). The processor also includes logic circuitry configured to increase performance of active processor cores when an inactive processor core count meets or exceeds the first threshold. The processor may also include a second storage location configured to store a second threshold associated with a second boost P-State. The logic circuitry may be configured to compare the inactive processor core count to the first and second thresholds, select one of the first and second boost P-States and increase performance of active processor cores based on the selected boost P-State. | 06-21-2012 |
20120159198 | PROCESSOR POWER LIMIT MANAGEMENT - A processor power limiter and method is provided. The processor includes a first programmable location configured to store a processor power target. A power monitor is configured to estimate a measured power dissipation within the processor. A power controller is configured to adjust a processor power parameter based on the power target and the measured power dissipation. The processor may include an interface for an operating system. A second programmable location may be configured to store a software processor power target accessible by the operating system. The processor may also include a sideband interface for an external agent. A third programmable location may be configured to store an agent processor power target accessible by the external agent. The power controller may be configured to adjust a processor core voltage and/or frequency such that the measured dissipation stays below the processor power target, software processor power target and the agent processor power target. | 06-21-2012 |
20140062562 | CONSTRAINING CLOCK SKEW IN A RESONANT CLOCKED SYSTEM - An integrated circuit includes a plurality of resonant clock domains of a resonant clock network. Each resonant clock domain has at least one clock driver that supplies a portion of clock signal to an associated resonant clock domain. The resonant clock network operates in a resonant mode with inductors connected to pairs of resonant clock domains at boundaries between the resonant clock domains. Each inductor forms an LC circuit with clock load capacitance in the pair of resonant clock domains to which the inductor is connected. | 03-06-2014 |
20140062563 | CONTROLLING IMPEDANCE OF A SWITCH USING HIGH IMPEDANCE VOLTAGE SOURCES TO PROVIDE MORE EFFICIENT CLOCKING - A clock system of an integrated circuit includes first and second transistors forming a switch that is used when switching the clock system between a resonant mode of operation and a non-resonant mode of operation. An inductor forms a resonant circuit with capacitance of the clock system in resonant mode. The switch receives a clock signal and supplies the clock signal to the inductor when the switch is closed and disconnects the inductor from the clock system when the switch is open. First and second high impedance voltage sources supply respective first and second voltages to the switch and a gate voltage of the first transistor transitions with the clock signal around the first voltage and a gate voltage of the second transistor transitions with the clock signal around the second voltage such that near constant overdrive voltages are maintained for the first and second transistors. | 03-06-2014 |
20140062564 | PROGRAMMABLE CLOCK DRIVER - A clock driver circuit supplies a clock signal with a drive strength determined according to one or more control signals supplied to the clock driver that vary during run-time. The clock driver is operated with a first drive strength in a non-resonant mode of operation of an associated clock network and with a second drive strength in a resonant mode of operation of the associated clock network, the first drive strength being higher than the second drive strength. | 03-06-2014 |
20140062565 | CLOCK DRIVER FOR FREQUENCY-SCALABLE SYSTEMS - A clock driver for a resonant clock network includes a delay circuit that receives and supplies a delayed clock signal. A first transistor is coupled to receive a first pulse control signal and supply an output clock node of the clock driver. An asserted edge of the first control signal is responsive to the falling edge of the delayed clock signal. A second transistor is coupled to receive a second control signal and to supply the output clock node of the clock driver. An asserted edge of the second control signal is responsive to a rising edge of the delayed clock signal. | 03-06-2014 |
20140181536 | USING TEMPERATURE MARGIN TO BALANCE PERFORMANCE WITH POWER ALLOCATION - A method and apparatus using temperature margin to balance performance with power allocation. Nominal, middle and high power levels are determined for compute elements. A set of temperature thresholds are determined that drive the power allocation of the compute elements towards a balanced temperature profile. For a given workload, temperature differentials are determined for each of the compute elements relative the other compute elements, where the temperature differentials correspond to workload utilization of the compute element. If temperature overhead is available, and a compute element is below a temperature threshold, then particular compute elements are allocated power to match or drive toward the balanced temperature profile. | 06-26-2014 |
20150268707 | USING TEMPERATURE MARGIN TO BALANCE PERFORMANCE WITH POWER ALLOCATION - A method and apparatus using temperature margin to balance performance with power allocation. Nominal, middle and high power levels are determined for compute elements. A set of temperature thresholds are determined that drive the power allocation of the compute elements towards a balanced temperature profile. For a given workload, temperature differentials are determined for each of the compute elements relative the other compute elements, where the temperature differentials correspond to workload utilization of the compute element. If temperature overhead is available, and a compute element is below a temperature threshold, then particular compute elements are allocated power to match or drive toward the balanced temperature profile. | 09-24-2015 |
20150268713 | ENERGY-AWARE BOOSTING OF PROCESSOR OPERATING POINTS FOR LIMITED DURATION WORKLOADS - The operating point of a processing unit is controlled based on the power consumption (i.e., the rate of energy consumption) associated with a workload, wherein low power consumption may indicate short-duration workloads with idle phases and high power consumption may indicate long, sustained workloads. Energy credits are accumulated while a drain rate of a battery is lower than a threshold drain rate and the energy credits are consumed while the drain rate is higher than the threshold drain rate. The operating point of the processing unit may be increased from a first operating point to a second operating point in response to the energy credits exceeding a first threshold. The operating point of the processing unit may be decreased from the second operating point to the first operating point in response to the energy credits falling below a second threshold. | 09-24-2015 |
20150286550 | METHOD AND SYSTEM OF SAMPLING TO AUTOMATICALLY SCALE DIGITAL POWER ESTIMATES WITH FREQUENCY - A method for automatically scaling estimates of digital power consumed by a portion of an integrated circuit (IC) device by the operating frequency of the portion of the IC are described herein. The method may include obtaining an energy value which may correspond to an amount of energy used by the portion of the IC. A cumulative energy value may be generated by repeatedly, at a frequency proportional to the operating frequency of the portion of the IC, obtaining energy values and adding each obtained energy value to a sum of energy values for the portion of the IC. The cumulative energy value may be sampled at a time sample interval to generate an estimate of the portion of the IC's digital power consumption that is automatically scaled with the operating frequency of the portion of the IC. | 10-08-2015 |
20150331433 | HYBRID SYSTEM AND METHOD FOR DETERMINING PERFORMANCE LEVELS BASED ON THERMAL CONDITIONS WITHIN A PROCESSOR - A system and method for efficient management of operating modes within an integrated circuit (IC) for optimal power and performance targets. A semiconductor chip includes one or more processing units each of which operates with respective operating parameters. One or more temperature sensors are included to measure a temperature of the one or more processing units during operation. When the measured temperature exceeds a threshold, a power manager on the chip determines a temperature headroom utilizing temperature values based on worst-case ambient temperature. When the measured temperature does not exceed the threshold, the power manager determines the temperature headroom utilizing at least one temperature value based on room ambient temperature. Following, the power manager adjusts the respective operating parameters based on at least the temperature headroom. | 11-19-2015 |
20150378411 | CALIBRATING A POWER SUPPLY USING POWER SUPPLY MONITORS - A processing system includes one or more power supply monitors (PSMs) to measure one or more first voltages corresponding to one or more locations in the processing system. The measurements are performed concurrently with the processing system executing one or more code loops. The processing system also includes calibration logic to modify a second voltage provided to the processing system based on a comparison of a reference voltage and the one or more first voltages. The reference voltage is determined based on previous execution of the one or more code loops by the processing system. | 12-31-2015 |