Patent application number | Description | Published |
20120206012 | ELECTROMECHANICAL DEVICES AND METHODS FOR FABRICATION OF THE SAME - A fabricated electromechanical device is disclosed herein. An exemplary device includes, a substrate, at least one layer of a high-transconductance material separated from the substrate by a dielectric medium, a first electrode in electrical contact with the at least one layer of a high-transconductance material and separated from the substrate by at least one first supporting member, a second electrode in electrical contact with the layer of a high-transconductance material and separated from the substrate by at least one second supporting member, where the first electrode is electrically separate from the second electrode, and a third electrode separated from the at least one layer of high-transconductance material by a dielectric medium and separated from each of the first electrode and the second electrode by a dielectric medium. | 08-16-2012 |
20130133031 | Retention Based Intrinsic Fingerprint Identification Featuring A Fuzzy Algorithm and a Dynamic Key - A random intrinsic chip ID generation employs a retention fail signature. A 1 | 05-23-2013 |
20140100807 | CHIP AUTHENTICATION USING MULTI-DOMAIN INTRINSIC IDENTIFIERS - Embodiments of the present invention provide a chip authentication system using multi-domain intrinsic identifiers. Multiple intrinsic identifiers taken from multiple domains (areas or sections of the chip) are compared against the intrinsic identifiers collected during the manufacture of the chip. If at least one intrinsic identifier matches those collected during manufacture, the chip may be designated as authentic. | 04-10-2014 |
20140165141 | SELF-AUTHENTICATING CHIP - Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values. | 06-12-2014 |
20140319600 | TSV Structure With A Built-In U-Shaped FET Transistor For Improved Characterization - A through-the silicon via (TSV) structure providing a built-in TSV U-shaped FET that includes an annular gate shaped as a TSV partially embedded in a substrate, the annular gate having an inner and an outer surface bound by an oxide layer; a drain formed on an isolated epitaxial layer on top of the substrate conformally connecting the gate oxide layer surrounding the inner annular surface of the TSV; a source partially contacting said gate oxide layer conformally contacting gate oxide layer surrounding the outer surface of the TSV. | 10-30-2014 |
20150163211 | UNCLONABLE ID BASED CHIP-TO-CHIP COMMUNICATION - A first copy of an intrinsic ID of a first node may be stored on a second node. The first node may receive a challenge that causes it to generate a second copy of its intrinsic ID. The second copy and a random value may be used as inputs of a function to generate a first code. The first code is transmitted to the second node. The second node decodes the first code using its local copies of the random value and/or the intrinsic ID. The second node checks the decoded information against its local information and authenticates the first node if there is a match. | 06-11-2015 |
20150186639 | SELF-AUTHENTICATING CHIP - Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values. | 07-02-2015 |
20150278551 | PHYSICALLY UNCLONABLE FUSE USING A NOR TYPE MEMORY ARRAY - A method for identifying an unclonable chip uses hardware intrinsic keys and authentication responses employing intrinsic parameters of memory cells invariant and unique to the unclonable chip, wherein intrinsic parameters that characterize the chip can extend over its lifetime. The memory cells having a charge-trap behavior are arranged in an NOR type memory array, allowing to create a physically unclonable fuse (PUF) generation using non-programmed memory cells, while stringing non-volatile bits in programmed memory cells. The non-volatile memory cell bits are used for error-correction-code (ECC) for the generated PUF. The invention can further include a public identification using non-volatile bits, allowing hand shaking authentication using computer with dynamic challenge. | 10-01-2015 |