Patent application number | Description | Published |
20140165269 | FLEXIBLE COMPUTING FABRIC - A flexible computing fabric and a method of forming thereof. The flexible computing fabric includes an electronic substrate including one or more channels and including at least two ends. At least one computational element is mounted on the electronic substrate between the two ends and at least one functional element is mounted on the electronic substrate between the two ends. The channels form an interconnect between the elements. In addition, the electronic substrate is flexible and exhibits a flexural modulus in the range of 0.1 GPa to 30 GPa. | 06-19-2014 |
20140168355 | WEARABLE IMAGING SENSOR FOR COMMUNICATIONS - A wearable image sensor is described. In one example, an apparatus includes a camera to capture images with a wide field of view, a data interface to send camera images to an external device, and a power supply to power the camera and the data interface. The camera, data interface, and power supply are attached to a garment that is wearable. | 06-19-2014 |
20140191419 | 3D INTEGRATED CIRCUIT PACKAGE WITH WINDOW INTERPOSER - 3D integrated circuit packages with window interposers and methods to form such semiconductor packages are described. For example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer having a window is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in the window of the interposer and interconnected to the top semiconductor die. In another example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in a same plane as the interposer and interconnected to the top semiconductor die. | 07-10-2014 |
20140205851 | MAGNETIC CONTACTS FOR ELECTRONICS APPLICATIONS - An interconnect structure for electrically joining two surfaces includes magnetic attachment structures and an anisotropic conductive adhesive (ACA). Magnetic attachment structures on a first surface are magnetically attracted to magnetic attachment structures on a second surface. Opposing magnetic attachment structures are joined via an ACA, which conducts electricity when compressed, and is electrically insulating when not compressed. The magnetic attraction between opposing magnetic attachment structures generates a sufficient force to maintain compression of the intervening ACA in order to sustain a desired level of electrical conductivity between the first surface and second surface. A method for joining two surfaces using the interconnect structure is disclosed. Additionally, a magnetic anisotropic conductive adhesive having magnetic conductive particles dispersed therein is disclosed. | 07-24-2014 |
20140264910 | INTERCONNECT STRUCTURES WITH POLYMER CORE - Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed. | 09-18-2014 |
20140332956 | INTEGRATED CIRCUIT PACKAGE WITH SPATIALLY VARIED SOLDER RESIST OPENING DIMENSION - An integrated circuit (IC) package stack with a first and second substrate interconnected by solder further includes solder resist openings (SRO) of mixed lateral dimension are spatially varied across an area of the substrates. In embodiments, SRO dimension is varied between at least two different diameters as a function of an estimated gap between the substrates that is dependent on location within the substrate area. In embodiments where deflection in at least one substrate reduces conformality between the substrates, a varying solder joint height is provided from a fixed volume of solder by reducing the lateral dimensioning of the SRO in regions of larger gap relative to SRO dimensions in regions of smaller gap. In embodiments, the first substrate may be any of an IC chip, package substrate, or interposer while the second substrate may be any of another IC chip, package substrate, interposer, or printed circuit board (PCB). | 11-13-2014 |
20150108204 | INTEGRATED CIRCUIT PACKAGE WITH SPATIALLY VARIED SOLDER RESIST OPENING DIMENSION - An integrated circuit (IC) package stack with a first and second substrate interconnected by solder further includes solder resist openings (SRO) of mixed lateral dimension are spatially varied across an area of the substrates. In embodiments, SRO dimension is varied between at least two different diameters as a function of an estimated gap between the substrates that is dependent on location within the substrate area. In embodiments where deflection in at least one substrate reduces conformality between the substrates, a varying solder joint height is provided from a fixed volume of solder by reducing the lateral dimensioning of the SRO in regions of larger gap relative to SRO dimensions in regions of smaller gap. In embodiments, the first substrate may be any of an IC chip, package substrate, or interposer while the second substrate may be any of another IC chip, package substrate, interposer, or printed circuit board (PCB). | 04-23-2015 |
20150162313 | INTERCONNECT STRUCTURES WITH POLYMER CORE - Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed. | 06-11-2015 |