Patent application number | Description | Published |
20100143480 | TRICALCIUM PHOSPHATE COARSE PARTICLE COMPOSITIONS AND METHODS FOR MAKING THE SAME - Methods for preparing a tricalcium phosphate coarse particle composition are provided. Aspects of the methods include converting an initial tricalcium phosphate particulate composition to hydroxyapatite, sintering the resultant hydroxyapatite to produce a second tricalcium phosphate composition and then mechanically manipulating the second tricalcium phosphate composition to produce a tricalcium phosphate coarse particle composition. The subject methods and compositions produced thereby find use in a variety of applications. | 06-10-2010 |
20110073006 | RAPID SETTING HIGH STRENGTH CALCIUM PHOSPHATE CEMENTS COMPRISING CYCLODEXTRINS - Rapid setting high strength calcium phosphate cements and methods of using the same are provided. Aspects of the cements include fine and coarse calcium phosphate particulate reactants and a cyclodextrin which, upon combination with a setting fluid, produce a flowable composition that rapidly sets into a high strength product. The flowable compositions find use in a variety of different applications, including the repair of hard tissue defects, e.g., bone defects such as fractures. | 03-31-2011 |
20110268815 | TEMPERATURE-INSENSITIVE CALCIUM PHOSPHATE CEMENTS - Temperature-insensitive calcium phosphate cements and methods of using the same are provided. Aspects of the cements include a dry component having fine and coarse calcium phosphate particulate reactants and a setting fluid which includes a cellulose. The dry component and setting fluid may be combined over a broad temperature range to produce a flowable composition. The resultant flowable composition finds use in a variety of different applications, including the repair of hard tissue defects, e.g., bone defects such as fractures. | 11-03-2011 |
20120000394 | Tricalcium Phosphate Coarse Particle Compositions and Methods for Making the Same - Methods for preparing a tricalcium phosphate coarse particle composition are provided. Aspects of the methods include converting an initial tricalcium phosphate particulate composition to hydroxyapatite, sintering the resultant hydroxyapatite to produce a second tricalcium phosphate composition and then mechanically manipulating the second tricalcium phosphate composition to produce a tricalcium phosphate coarse particle composition. The subject methods and compositions produced thereby find use in a variety of applications. | 01-05-2012 |
20120115780 | Porogen Containing Calcium Phosphate Cement Compositions - Porogen containing calcium phosphate cement compositions are provided. Aspects of the cement compositions include a dry calcium phosphate reactant component, a setting fluid component and a porogen component. The porogen component includes at least first and second porogens having different pore forming profiles. Aspects of the invention include combining the cement components to produce a settable composition. Aspects of the invention further include the settable compositions themselves as well as kits for preparing the same. Methods and compositions as described herein find use in a variety of applications, including hard tissue repair applications. | 05-10-2012 |
20130017233 | Tricalcium Phosphate Coarse Particle Compositions and Methods for Making the Same - Methods for preparing a tricalcium phosphate coarse particle composition are provided. Aspects of the methods include converting an initial tricalcium phosphate particulate composition to hydroxyapatite, sintering the resultant hydroxyapatite to produce a second tricalcium phosphate composition and then mechanically manipulating the second tricalcium phosphate composition to produce a tricalcium phosphate coarse particle composition. The subject methods and compositions produced thereby find use in a variety of applications. | 01-17-2013 |
20130165540 | Porous Calcium Phospate Granules and Methods of Making and Using the Same - Porous calcium phosphate granules and methods of making the same are provided. Embodiments of the methods include producing a solid spherical granule precursor that includes: (i) a calcium phosphate component; and (ii) a porogen component; and (b) removing the porogen component from the solid spherical granule precursor to produce a spherical porous calcium phosphate granule. Granules of the invention find use in a variety of different applications. | 06-27-2013 |
20140010880 | Tricalcium Phosphate Coarse Particle Compositions and Methods for Making the Same - Methods for preparing a tricalcium phosphate coarse particle composition are provided. Aspects of the methods include converting an initial tricalcium phosphate particulate composition to hydroxyapatite, sintering the resultant hydroxyapatite to produce a second tricalcium phosphate composition and then mechanically manipulating the second tricalcium phosphate composition to produce a tricalcium phosphate coarse particle composition. The subject methods and compositions produced thereby find use in a variety of applications. | 01-09-2014 |
20140202359 | Rapid Setting High Strength Calcium Phosphate Cements Comprising Cyclodextrins - Rapid setting high strength calcium phosphate cements and methods of using the same are provided. Aspects of the cements include fine and coarse calcium phosphate particulate reactants and a cyclodextrin which, upon combination with a setting fluid, produce a flowable composition that rapidly sets into a high strength product. The flowable compositions find use in a variety of different applications, including the repair of hard tissue defects, e.g., bone defects such as fractures. | 07-24-2014 |
Patent application number | Description | Published |
20100250869 | VIRTUALIZATION SYSTEM USING HARDWARE ASSISTANCE FOR SHADOW PAGE TABLE COHERENCE - One embodiment of the present invention includes a method for maintaining a shadow page table in at least partial correspondence with guest page mappings of a guest computation. The method marking with a traced write indication at least those entries of the shadow page table that map physical memory locations which themselves encode the guest page mappings, the marking identifying, for a hardware facility, a subset of memory access targets for which updates are to be recorded in a guest write buffer accessible to the virtualization system. Responsive to a coherency-inducing operation of the guest computation, the method reads from the guest write buffer and introduces corresponding updates into the shadow page table. | 09-30-2010 |
20100250895 | HARDWARE ASSISTANCE FOR SHADOW PAGE TABLE COHERENCE WITH GUEST PAGE MAPPINGS - Some embodiments of the present invention include an execution unit of a processor and a memory management unit interposed between the execution unit and an interface to memory suitable for storage of both guest page tables maintained by a guest operating system and shadow page tables maintained generally in correspondence with the guest page tables by virtualization software. The memory management unit is configured to walk in-memory data structures that encode the shadow page tables, to access entries of the shadow page tables and, based thereon or on a cached representation of page mappings therein, to perform virtual-to-physical address translations relative to memory targets of instructions executed by the execution unit. The memory management unit is responsive to a shadowed write indication coded in association with either an entry of the shadow page tables or a cached representation of a page mapping therein used to perform the virtual-to-physical address translation for a write-type one of the instructions that targets an entry of one of the guest page tables. The memory management unit is configured to complete the memory access of the write-type instruction that targets the guest page table entry and to store in a buffer, information sufficient to allow the virtualization software to later update an entry of the shadow page tables in correspondence therewith. | 09-30-2010 |
20120059973 | HARDWARE ASSISTANCE FOR SHADOW PAGE TABLE COHERENCE WITH GUEST PAGE MAPPINGS - Some embodiments of the present invention include a memory management unit (MMU) configured to, in response to a write access targeting a guest page mapping of a guest virtual page number (GVPN) to a guest physical page number (GPPN) within a guest page table, identify a shadow page mapping that associates the GVPN with a physical page number (PPN). The MMU is also configured to determine whether a traced write indication is associated with the shadow page mapping and, if so, record update information identifying the targeted guest page mapping. The update information is used to reestablish coherence between the guest page mapping and the shadow page mapping. The MMU is further configured to perform the write access. | 03-08-2012 |
20120278588 | HARDWARE ASSISTANCE FOR PAGE TABLE COHERENCE WITH GUEST PAGE MAPPINGS - Some embodiments of the present invention include a memory management unit (MMU) configured to, in response to a write access targeting a guest page mapping of a guest virtual page number (GVPN) to a guest physical page number (GPPN) within a guest page table, identify a first page mapping that associates the GVPN with a physical page number (PPN). The MMU is also configured to determine whether a traced write indication is associated with the first page mapping and, if so, record update information identifying the targeted guest page mapping. The update information is used to reestablish coherence between the guest page mapping and the first page mapping. The MMU is further configured to perform the write access. | 11-01-2012 |
20130067245 | SOFTWARE CRYPTOPROCESSOR - Security of information—both code and data—stored in a computer's system memory is provided by an agent loaded into and at run time resident in a CPU cache. Memory writes from the CPU are encrypted by the agent before writing and reads into the CPU are decrypted by the agent before they reach the CPU. The cache-resident agent also optionally validates the encrypted information stored in the system memory. Support for I/O devices and cache protection from unsafe DMA of the cache by devices is also provided. | 03-14-2013 |
20130262798 | VIRTUALIZATION SYSTEM USING HARDWARE ASSISTANCE FOR SHADOW PAGE TABLE COHERENCE - One embodiment of the present invention includes a method for maintaining a shadow page table in at least partial correspondence with guest page mappings of a guest computation. The method marking with a traced write indication at least those entries of the shadow page table that map physical memory locations which themselves encode the guest page mappings, the marking identifying, for a hardware facility, a subset of memory access targets for which updates are to be recorded in a guest write buffer accessible to the virtualization system. Responsive to a coherency-inducing operation of the guest computation, the method reads from the guest write buffer and introduces corresponding updates into the shadow page table. | 10-03-2013 |
20150032935 | VIRTUALIZATION SYSTEM USING HARDWARE ASSISTANCE FOR PAGE TABLE COHERENCE - One embodiment of the present invention includes a method for maintaining a shadow page table in at least partial correspondence with guest page mappings of a guest computation. The method marking with a traced write indication at least those entries of the shadow page table that map physical memory locations which themselves encode the guest page mappings, the marking identifying, for a hardware facility, a subset of memory access targets for which updates are to be recorded in a guest write buffer accessible to the virtualization system. Responsive to a coherency-inducing operation of the guest computation, the method reads from the guest write buffer and introduces corresponding updates into the shadow page table. | 01-29-2015 |
20150067265 | System and Method for Partitioning of Memory Units into Non-Conflicting Sets - A system and method of operation exploit the limited associativity of a single cache set to force observable cache evictions and discover conflicts. Loads are issued to input memory addresses, one at a time, until a cache eviction is detected. After observing a cache eviction on a load from an address, that address is added to a data structure representing the current conflict set. The cache is then flushed, and loads are issued to all addresses in the current conflict set, so that all known conflicting addresses are accessed first, ensuring that the next cache miss will occur on a different conflicting address. The process is repeated, issuing loads from all input memory addresses, incrementally finding conflicting addresses, one by one. Memory addresses that conflict in the cache belong to the same partition, whereas memory addresses belonging to different partitions do not conflict. | 03-05-2015 |
20150227744 | ATTESTATION USING A COMBINED MEASUREMENT AND ITS CONSTITUENT MEASUREMENTS - An attestation system for asserting and verifying assertions of a known-good state of a computer system is provided. The attestation system allows a challenger and a prover to conduct an attestation so that the challenger can verify an assertion of the prover. To conduct the attestation, the prover sends, as an assertion of its state, a combined measurement of resources along with a constituent measurement of each resource to the challenger. The challenger verifies the assertion by verifying that the asserted constituent measurements represent known-good measurements and verifying that the asserted combined measurement can be generated from the asserted constituent measurements. To verify the asserted constituent measurements, the challenger determines whether each asserted constituent measurement for a resource is a known-good measurement for that resource. To verify the asserted combined measurement, the challenger generates a combined measurement from the asserted constituent measurements received from the prover. | 08-13-2015 |
20150269091 | SECURE SUPPORT FOR I/O IN SOFTWARE CRYPTOPROCESSOR - Methods and systems for securing sensitive data from security risks associated with direct memory access (“DMA”) by input/output (“I/O”) devices are provided. An enhanced software cryptoprocessor system secures sensitive data using various techniques, including (1) protecting sensitive data by preventing DMA by an I/O device to the portion of the cache that stores the sensitive data, (2) protecting device data by preventing cross-device access to device data using DMA isolation, and (3) protecting the cache by preventing the pessimistic eviction of cache lines on DMA writes to main memory. | 09-24-2015 |