Patent application number | Description | Published |
20090070524 | NON-SNOOP READ/WRITE OPERATIONS IN A SYSTEM SUPPORTING SNOOPING - Techniques that may utilize generic tracker structures to provide data coherency in a multi-node system that supports non-snoop read and write operations. The trackers may be organized as a two-dimensional queue structure that may be utilized to resolve conflicting read and/or write operations. Multiple queues having differing associated priorities may be utilized. | 03-12-2009 |
20090292879 | Nodma cache - A NoDMA cache including a super page field. The super page field indicates when a set of pages contain protected information. The NoDMA cache is used by a computer system to deny I/O device access to protected information in system memory. | 11-26-2009 |
20100005245 | SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL WRITES AND NON-SNOOP ACCESSES - A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, when a conflict associated with a partial memory access, such as a partial write, is detected, a write-back phase is inserted at the conflict phase to write-back the partial data to a home agent. Examples messages to initiate a write-back phase at a conflict phase include: an Acknowledge Conflict Write-back message to acknowledge a conflict and provide a write-back marker at the beginning of the conflict phase, a write-back marker message before the conflict phase, a write-back marker message within the conflict phase, a write-back marker message after the conflict phase, and a postable message after the conflict phase. | 01-07-2010 |
20100005246 | SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND NON-SNOOP ACCESSES - A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data. | 01-07-2010 |
20100115312 | TECHNIQUES FOR ENTERING A LOW-POWER LINK STATE - Techniques to cause a point-to-point link between system components to engage in a negotiation process that may lead to the link transitioning from an active state in which data may be transmitted between system components to a low power state where data may not be transmitted. The negotiation process may occur between each pair of nodes within an electronic system that are interconnected via point-to-point link. The negotiation may ensure that there are no pending transactions or transactions that may occur within an upcoming period of time. Through this negotiation each component acknowledges and agrees to transition the link to the low power state. | 05-06-2010 |
20100146200 | NON-SNOOP READ/WRITE OPERATIONS IN A SYSTEM SUPPORTING SNOOPING - Techniques that may utilize generic tracker structures to provide data coherency in a multi-node system that supports non-snoop read and write operations. The trackers may be organized as a two-dimensional queue structure that may be utilized to resolve conflicting read and/or write operations. Multiple queues having differing associated priorities may be utilized. | 06-10-2010 |
20110161702 | TECHNIQUES FOR ENTERING A LOW-POWER LINK STATE - Techniques to cause a point-to-point link between system components to engage in a negotiation process that may lead to the link transitioning from an active state in which data may be transmitted between system components to a low power state where data may not be transmitted. The negotiation process may occur between each pair of nodes within an electronic system that are interconnected via point-to-point link. The negotiation may ensure that there are no pending transactions or transactions that may occur within an upcoming period of time. Through this negotiation each component acknowledges and agrees to transition the link to the low power state. | 06-30-2011 |
20110238778 | Reducing Packet Size In A Communication Protocol - In one embodiment, the present invention includes a processor that can generate data packets for transmission to an agent, where the processor can generate a data packet having a command portion including a first operation code to encode a transaction type for the data packet and a second operation code to encode a processor-specific operation. This second operation code can encode many different features such as an indication that the data packet is of a smaller size than a standard packet, in order to reduce bandwidth. This operation code can also identify an operation to be performed by a destination agent coupled to the agent. Other embodiments are described and claimed. | 09-29-2011 |
20120079156 | IMPLEMENTING QUICKPATH INTERCONNECT PROTOCOL OVER A PCIe INTERFACE - Methods and apparatus for implementing the Intel QuickPath Interconnect® (QPI) protocol over a PCIe interface. The upper layers of the QPI protocol are implemented over a physical layer of the PCIe interface via use of QPI data bit mappings onto corresponding PCIe x16, x8, and x4 lane configurations. A QPI link layer to PCIe physical layer interface is employed to abstract the QPI link, routing, and protocol layers from the underlying PCIe physical layer (and corresponding PCIe interface circuitry), enabling QPI protocol messages to be employed over PCIe hardware. Thus, QPI functionality, such as support for coherent memory transactions, may be implemented over PCIe interface circuitry. | 03-29-2012 |
20120317369 | SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND NON-SNOOP ACCESSES - A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data. | 12-13-2012 |
20130103783 | Reducing Packet Size In A Communication Protocol - In one embodiment, the present invention includes a processor that can generate data packets for transmission to an agent, where the processor can generate a data packet having a command portion including a first operation code to encode a transaction type for the data packet and a second operation code to encode a processor-specific operation. This second operation code can encode many different features such as an indication that the data packet is of a smaller size than a standard packet, in order to reduce bandwidth. This operation code can also identify an operation to be performed by a destination agent coupled to the agent. Other embodiments are described and claimed. | 04-25-2013 |
20130268711 | RAW MEMORY TRANSACTION SUPPORT - Methods, systems, and apparatus for implementing raw memory transactions. An SoC is configured with a plurality of nodes coupled together forming a ring interconnect. Processing cores and memory cache components are operatively coupled to and co-located at respective nodes. The memory cache components include a plurality of last level caches (LLC's) operating as a distributed LLC and a plurality of home agents and caching agents employed for supporting coherent memory transactions. Route-back tables are used to encode memory transactions requests with embedded routing data that is implemented by agents that facilitate data transfers between link interface nodes and memory controllers. Accordingly, memory request data corresponding to raw memory transactions may be routed back to requesting entities using headerless packets. | 10-10-2013 |
20130346666 | TUNNELING PLATFORM MANAGEMENT MESSAGES THROUGH INTER-PROCESSOR INTERCONNECTS - Methods and apparatus for tunneling platform management messages through inter-processor interconnects. Platform management messages are received from a management entity such as a management engine (ME) at a management component of a first processor targeted for a managed device operatively coupled to a second processor. Management message content is encapsulated in a tunnel message that is tunneled from the first processor to a second management component in the second processor via a socket-to-socket interconnect link between the processors. Once received at the second management component the encapsulated management message content is extracted and the original management message is recreated. The recreated management message is then used to manage the targeted device in a manner similar to if the ME was directly connected to the second processor. The disclosed techniques enable management of platform devices operatively coupled to processors in a multi-processor platform via a single management entity. | 12-26-2013 |
20140112339 | HIGH PERFORMANCE INTERCONNECT - A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state | 04-24-2014 |
20140115268 | HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL - A coherence protocol message is sent corresponding to a particular cache line. A potential conflict involving the particular cache line is identified and a forward request is sent to a home agent to identify the potential conflict. A forward response can be received in response to the forward request from the home agent and a response to the conflict can be determined. | 04-24-2014 |
20140115275 | SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND NON-SNOOP ACCESSES - A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data. | 04-24-2014 |
20140115420 | HIGH PERFORMANCE INTERCONNECT LINK LAYER - Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots. | 04-24-2014 |
20140372658 | MULTIPLE TRANSACTION DATA FLOW CONTROL UNIT FOR HIGH-SPEED INTERCONNECT - Methods, apparatus, and systems, for transporting data units comprising multiple pieces of transaction data over high-speed interconnects. A flow control unit, called a KTI (Keizer Technology Interface) Flit, is implemented in a coherent multi-layer protocol supporting coherent memory transactions. The KTI Flit has a basic format that supports use of configurable fields to implement KTI Flits with specific formats that may be used for corresponding transactions. In one aspect, the KTI Flit may be formatted as multiple slots used to support transfer of multiple respective pieces of transaction data in a single Flit. The KTI Flit can also be configured to support various types of transactions and multiple KTI Flits may be combined into packets to support transfer of data such as cache line transfers. | 12-18-2014 |
20150089161 | HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL - A coherence protocol message is sent corresponding to a particular cache line. A potential conflict involving the particular cache line is identified and a forward request is sent to a home agent to identify the potential conflict. A forward response can be received in response to the forward request from the home agent and a response to the conflict can be determined. | 03-26-2015 |