Patent application number | Description | Published |
20080304432 | System and method for an energy efficient RF transceiver - An energy efficient radio having a clocking system utilizing two clocks with very different precision and power characteristics. In another aspect, the time that a radio spends on listening/receiving is optimized so that energy is not wasted when there is no need to keep receiving. In another aspect, to further improve the energy efficiency, two receive portions with drastic difference in power consumption, instead of a single receive portion as is used in a typical wireless receiver, and are used to process different parts of a received packet. | 12-11-2008 |
20090046611 | System and method for media access control for a duty cycle network - A system and method for medium access control in a wireless communication network including the use of packets having a header and plural data portions, acknowledgement request features, corrupt packet identification, and adaptive duty cycling. | 02-19-2009 |
20090080460 | System and method for providing bandwidth signaling across cryptographic boundaries in a network - The use of Protocol Enhancing Proxies (PEPs) and HAIPE encryption has traditionally been mutually exclusive. IP-layer encryption renders the upper layers, such as TCP, unavailable to the PEP. By integrating the IP layer encryption into the modem and using additive or multiplicative increase and decrease signals as bandwidth notification, signaling is provided across the cryptographic boundary to support the use of a bandwidth aware PEP in a network protected by IP-layer encryption. | 03-26-2009 |
20090119086 | System and method for clock modeling in discrete-event simulation - Local clock modeling for a discrete event simulator is described. A local clock generator provides realistic clock characteristics in terms of clock precision and clock drift and clock mapping utilities provide API for other modules and/or protocols in the discrete event simulator to schedule events on local clocks instead of global clock of the simulator. | 05-07-2009 |
20140347978 | DYNAMIC ROUTING UNDER EXTREME COGNITIVE JAMMING ENVIRONMENTS - A system and methods for dynamic routing under extreme cognitive jamming environments are presented. Jammer signals emitted by a network protocol-aware cognitive jammer are scanned for at a router node in an ad-hoc wireless network, and jammer behaviors are detected based on signal characteristics of the jammer signals. A network dynamic pattern caused by the network protocol-aware cognitive jammer is classified based on the detected jammer behaviors observed over a period of time, and dynamic routing strategies of the first router node are adapted to achieve robust data delivery based on the network behavioral pattern. Data packets sent by the router node are routed to avoid nodes and routes that are affected by the jammer signals. | 11-27-2014 |
Patent application number | Description | Published |
20100009554 | Microelectronic interconnect element with decreased conductor spacing - A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines. | 01-14-2010 |
20100044860 | Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer - An interconnection element can include a substrate, e.g., a connection substrate, element of a package, circuit panel or microelectronic substrate, e.g., semiconductor chip, the substrate having a plurality of metal conductive elements such as conductive pads, contacts, bond pads, traces, or the like exposed at the surface. A plurality of solid metal posts may overlie and project away from respective ones of the conductive elements. An intermetallic layer can be disposed between the posts and the conductive elements, such layer providing electrically conductive interconnection between the posts and the conductive elements. Bases of the posts adjacent to the intermetallic layer can be aligned with the intermetallic layer. | 02-25-2010 |
20130186944 | MICROELECTRONIC SUBSTRATE OR ELEMENT HAVING CONDUCTIVE PADS AND METAL POSTS JOINED THERETO USING BOND LAYER - An interconnection element can include a substrate, e.g., a connection substrate, element of a package, circuit panel or microelectronic substrate, e.g., semiconductor chip, the substrate having a plurality of metal conductive elements such as conductive pads, contacts, bond pads, traces, or the like exposed at the surface. A plurality of solid metal posts may overlie and project away from respective ones of the conductive elements. An intermetallic layer can be disposed between the posts and the conductive elements, such layer providing electrically conductive interconnection between the posts and the conductive elements. Bases of the posts adjacent to the intermetallic layer can be aligned with the intermetallic layer. | 07-25-2013 |
20130341299 | Method of Making a Microelectronic Interconnect Element With Decreased Conductor Spacing - A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines. | 12-26-2013 |
20150087146 | MICROELECTRONIC INTERCONNECT ELEMENT WITH DECREASED CONDUCTOR SPACING - A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines. | 03-26-2015 |
Patent application number | Description | Published |
20140010282 | POWER AWARE VIDEO DECODING AND STREAMING - Methods and systems are disclosed for a mobile device to decode video based on available power and/or energy. For example, the mobile device may receive a media description file (MDF) from for a video stream from a video server. The MDF may include complexity information associated with a plurality of video segments. The complexity information may be related to the amount of processing power to be utilized for decoding the segment at the mobile device. The mobile device may determine at least one power metric for the mobile device. The mobile device may determine a first complexity level to be requested for a first video segment based on the complexity information from the MDF and the power metric. The mobile device may dynamically alter the decoding process to save energy based on the detected power/energy level. | 01-09-2014 |
20140010294 | CODEC ARCHITECTURE FOR MULTIPLE LAYER VIDEO CODING - Systems, methods, and instrumentalities are provided to implement video coding system (VCS). The VCS may be configured to receive a video signal, which may include one or more layers (e.g., a base layer (BL) and/or one or more enhancement layers (ELs)). The VCS may be configured to process a BL picture into an inter-layer reference (ILR) picture, e.g., using picture level inter-layer prediction process. The VCS may be configured to select one or both of the processed ILR picture or an enhancement layer (EL) reference picture. The selected reference picture(s) may comprise one of the EL reference picture, or the ILR picture. The VCS may be configured to predict a current EL picture using one or more of the selected ILR picture or the EL reference picture. The VCS may be configured to store the processed ILR picture in an EL decoded picture buffer (DPB). | 01-09-2014 |
20140036999 | FRAME PRIORITIZATION BASED ON PREDICTION INFORMATION - Priority information may be used to distinguish between different types of video data, such as different video packets or video frames. The different types of video data may be included in the same temporal level and/or different temporal levels in a hierarchical structure. A different priority level may be determined for different types of video data at the encoder and may be indicated to other processing modules at the encoder, or to the decoder, or other network entities such as a router or a gateway. The priority level may be indicated in a header of a video packet or signaling protocol. The priority level may be determined explicitly or implicitly. The priority level may be indicated relative to another priority or using a priority identifier that indicates the priority level. | 02-06-2014 |
20150229970 | METHODS AND SYSTEMS FOR PACKET DIFFERENTIATION - Methods and systems are disclosed facilitate differentiated QoS service for packets within a single packet stream. For example, extended QCI values may be used to differentiate service of video packets associated with different priorities. A flexible representation of QoS requirements/parameters is disclosed where QoS may be defined as a hyperspace that is a function of base QoS parameters. A WTRU may explicitly specify and/or request desired QoS parameters. A WTRU may be configured to perform one or more of video packet separation into a plurality of video packet sub-streams, merging of the video packet sub-streams, and/or reordering of the packets included in the video packet sub-streams. Techniques may be utilized to exposing more information to a data transmission network regarding the type of video packets (and/or other packets) being transmitted. | 08-13-2015 |
Patent application number | Description | Published |
20080290451 | Isolation structures for integrated circuits - A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate. | 11-27-2008 |
20090032876 | ESD protection for bipolar-CMOS-DMOS integrated circuit devices - An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage. | 02-05-2009 |
20090034136 | ESD protection for bipolar-CMOS-DMOS integrated circuit devices - An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage. | 02-05-2009 |
20090034137 | ESD protection for bipolar-CMOS-DMOS integrated circuit devices - An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage. | 02-05-2009 |
20090236683 | Isolation structures for integrated circuits - A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate. | 09-24-2009 |
Patent application number | Description | Published |
20090061505 | APPARATUS FOR SELECTIVE EXCITATION OF MICROPARTICLES - Nucleic acid microparticles are sequenced by performing a sequencing reaction on the microparticles using one or more selectively exciting the microparticles in an excitation pattern, optically imaging the microparticles at a resolution insufficient to resolve individual microparticles, and processing the optical images of the microparticles using information on the excitation pattern to determine the presence or absence of the optical signature, which indicates the sequence information of the nucleic acid. An apparatus for optical excitation of the microparticles comprises an optical fiber delivering a first laser beam, and an interference pattern generation module coupled to the optical fiber. The interference pattern generation module splits the first laser beam into second and third laser beams and generates the excitation pattern for selectively exciting the microparticles by interference between the second and third laser beams. | 03-05-2009 |
20090061526 | NUCLEIC ACID SEQUENCING BY SELECTIVE EXCITATION OF MICROPARTICLES - Nucleic acid microparticles are sequenced by performing a sequencing reaction on the microparticles using one or more reagents, selectively exciting the microparticles in an excitation pattern, optically imaging the microparticles at a resolution insufficient to resolve individual microparticles, and processing the optical images of the microparticles using information on the excitation pattern to determine the presence or absence of the optical signature, which indicates the sequence information of the nucleic acid. An apparatus for optical excitation of the microparticles comprises an optical fiber delivering a first laser beam, and an interference pattern generation module coupled to the optical fiber. The interference pattern generation module splits the first laser beam into second and third laser beams and generates the excitation pattern for selectively exciting the microparticles by interference between the second and third laser beams. | 03-05-2009 |
20140242683 | APPARATUS FOR SELECTIVE EXCITATION OF MICROPARTICLES - Nucleic acid microparticles are sequenced by performing a sequencing reaction on the microparticles using one or more reagents, selectively exciting the microparticles in an excitation pattern, optically imaging the microparticles at a resolution insufficient to resolve individual microparticles, and processing the optical images of the microparticles using information on the excitation pattern to determine the presence or absence of the optical signature, which indicates the sequence information of the nucleic acid. An apparatus for optical excitation of the microparticles comprises an interference pattern generation module that splits a first laser beam into second and third laser beams and generates the excitation pattern for selectively exciting the microparticles by interference between the second and third laser beams. | 08-28-2014 |
20140323325 | Molecular imaging and related methods - The present invention generally relates to imaging single molecules, or one or more collections of single molecules, and methods related to the imaging. In a method aspect, the present invention provides a method of imaging single molecules. The method comprises the steps of: a) exposing a test sample to a probe, wherein the probe comprises a first portion that specifically binds to a target molecule and a second portion that is detectable as the result of one or more chemical groups that interact with light at one or more wavelengths, wherein the probe binds to a target molecule to provide a complex; b) exposing the complex to one or more wavelengths of light that interact with the one or more chemical groups; c) detecting a result from the interacting of one or more wavelengths of light that interact with the one or more chemical groups to provide an image of one or more single molecules. The image possesses a resolution better than 450 nm over a view field area of at least 1×10 | 10-30-2014 |
Patent application number | Description | Published |
20100329827 | LINEAR VACUUM ROBOT WITH Z MOTION AND ARTICULATED ARM - There is described apparatus and methods for transporting and processing substrates including wafers as to efficiently produce at reasonable costs improved throughput as compared to systems in use today. A linear transport chamber includes linear tracks and robot arms riding on the linear tracks to linearly transfer substrates along the sides of processing chambers for feeding substrates into a controlled atmosphere through a load lock and then along a transport chamber as a way of reaching processing chambers. A four-axis robot arm is disclosed, capable of linear translation, rotation and articulation, and z-motion. | 12-30-2010 |
20120076626 | LINEAR VACUUM ROBOT WITH Z MOTION AND ARTICULATED ARM - There is described apparatus and methods for transporting and processing substrates including wafers as to efficiently produce at reasonable costs improved throughput as compared to systems in use today. A linear transport chamber includes linear tracks and robot arms riding on the linear tracks to linearly transfer substrates along the sides of processing chambers for feeding substrates into a controlled atmosphere through a load lock and then along a transport chamber as a way of reaching processing chambers. A four-axis robot arm is disclosed, capable of linear translation, rotation and articulation, and z-motion. | 03-29-2012 |
20130230370 | LINEAR VACUUM ROBOT WITH Z MOTION AND ARTICULATED ARM - There is described apparatus and methods for transporting and processing substrates including wafers as to efficiently produce at reasonable costs improved throughput as compared to systems in use today. A linear transport chamber includes linear tracks and robot arms riding on the linear tracks to linearly transfer substrates along the sides of processing chambers for feeding substrates into a controlled atmosphere through a load lock and then along a transport chamber as a way of reaching processing chambers. A four-axis robot arm is disclosed, capable of linear translation, rotation and articulation, and z-motion. | 09-05-2013 |
Patent application number | Description | Published |
20140010180 | METHOD AND APPARATUS FOR SERVICE ACCESS BARRING - The present invention is directed to a method and an apparatus for use in a wireless communication system. Specifically, the present invention is directed to a method and an apparatus of performing a network access procedure, the method comprising: receiving system information including Application-based (APP-based) information set, wherein the APP-based information set includes one or more APP-based information subsets, and each APP-based information subset is used to control network access per application; and performing the network access procedure under control of APP-based information subset corresponding to an application that causes the network access procedure. | 01-09-2014 |
20140064229 | METHOD AND APPARATUS FOR TRANSMITTING DISCOVERY SIGNAL IN WIRELESS COMMUNICATION SYSTEM - The present invention relates to a wireless communication system, and more specifically to a method and an apparatus for transmitting a discovery signal in a wireless communication system. According to one aspect of the present invention, a method for enabling a terminal for supporting multiple radio access technologies to perform communication includes the steps of: communicating first data to a base station; receiving first information for notifying the presence of a first AP from the first AP as at least one AP among a plurality of APs; and communicating second data using the first AP, wherein the first information is received by using a first resource as at least a part of all resources which the base station uses, a first radio access technology can be applied between the terminal and the base station, and a second radio access technology can be applied between the terminal and the first AP. | 03-06-2014 |
20140295832 | METHOD AND APPARATUS OF PERFORMING A DISCOVERY PROCEDURE - The present invention is directed to a method and an apparatus for use in a wireless communication system. Specifically, the present invention is directed to a method of performing a discovery procedure for a ProSe and an apparatus therefore, in which the method comprises: receiving first resource allocation information for plural ProSe channels from a base station via a broadcast signal; sensing the plural ProSe channels; transmitting a sensing result for the plural ProSe channels to the base station; receiving second resource allocation information indicating one of the plural ProSe channels from the base station via a unicast signal; and transmitting a discovery signal via the ProSe channel indicated by the second resource allocation information. | 10-02-2014 |
Patent application number | Description | Published |
20100127242 | TRANSPARENT ELECTRONICS BASED ON TRANSFER PRINTED CARBON NANOTUBES ON RIGID AND FLEXIBLE SUBSTRATES - Methods and devices for transparent electronics are disclosed. According to an embodiment, transparent electronics are provided based on transfer printed carbon nanotubes that can be disposed on both rigid and flexible substrates. Methods are provided to enable highly aligned single-walled carbon nanotubes (SWNTs) to be used in transparent electronics for achieving high carrier mobility while using low-temperature processing. According to one method, highly aligned nanotubes can be grown on a first substrate. Then, the aligned nanotubes can be transferred to a rigid or flexible substrate having pre-patterned gate electrodes. Source and drain electrodes can be formed on the transferred nanotubes. The subject devices can be integrated to provide logic gates and analog circuitry for a variety of applications. | 05-27-2010 |
20100133511 | Integrated Circuits Based on Aligned Nanotubes - Techniques, apparatus and systems are described for wafer-scale processing of aligned nanotube devices and integrated circuits. In one aspect, a method can include growing aligned nanotubes on at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate. The method can include transferring the grown aligned nanotubes onto a target substrate. Also, the method can include fabricating at least one device based on the transferred nanotubes. | 06-03-2010 |
20110017975 | ORGANIC OPTOELECTRONIC DEVICE ELECTRODES WITH NANOTUBES - An electrode for use in an organic optoelectronic device is provided. The electrode includes a thin film of single-wall carbon nanotubes. The film may be deposited on a substrate of the device by using an elastomeric stamp. The film may be enhanced by spin-coating a smoothing layer on the film and/or doping the film to enhance conductivity. Electrodes according to the present invention may have conductivities, transparencies, and other features comparable to other materials typically used as electrodes in optoelectronic devices. | 01-27-2011 |
20110101302 | WAFER-SCALE FABRICATION OF SEPARATED CARBON NANOTUBE THIN-FILM TRANSISTORS - Methods, materials, systems and apparatus are described for depositing a separated nanotube networks, and fabricating, separated nanotube thin-film transistors and N-type separated nanotube thin-film transistors. In one aspect, a method of depositing a wafer-scale separated nanotube networks includes providing a substrate with a dielectric layer. The method includes cleaning a surface of the wafer substrate to cause the surface to become hydrophilic. The cleaned surface of the wafer substrate is functionalized by applying a solution that includes linker molecules terminated with amine groups. High density, uniform separated nanotubes are assembled over the functionalized surface by applying to the functionalized surface a separated nanotube solution that includes semiconducting nanotubes. | 05-05-2011 |
20120261646 | Integrated Circuits Based on Aligned Nanotubes - Techniques, apparatus and systems are described for wafer-scale processing of aligned nanotube devices and integrated circuits one. In one aspect, a method can include growing aligned nanotubes on at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate. The method can include transferring the grown aligned nanotubes onto a target substrate. Also, the method can include fabricating at least one device based on the transferred nanotubes. | 10-18-2012 |
20130059406 | ORGANIC OPTOELECTRONIC DEVICE ELECTRODES WITH NANOTUBES - An electrode for use in an organic optoelectronic device is provided. The electrode includes a thin film of single-wall carbon nanotubes. The film may be deposited on a substrate of the device by using an elastomeric stamp. The film may be enhanced by spin-coating a smoothing layer on the film and/or doping the film to enhance conductivity. Electrodes according to the present invention may have conductivities, transparencies, and other features comparable to other materials typically used as electrodes in optoelectronic devices. | 03-07-2013 |
20130119348 | Radio Frequency Devices Based on Carbon Nanomaterials - RF transistors are fabricated at complete wafer scale using a nanotube deposition technique capable of forming high-density, uniform semiconducting nanotube thin films at complete wafer scale, and electrical characterization reveals that such devices exhibit gigahertz operation, linearity, and large transconductance and current drive. | 05-16-2013 |
20130134394 | Integrated Circuits Based on Aligned Nanotubes - Techniques, apparatus and systems are described for wafer-scale processing of aligned nanotube devices and integrated circuits. In one aspect, a method can include growing aligned nanotubes on at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate. The method can include transferring the grown aligned nanotubes onto a target substrate. Also, the method can include fabricating at least one device based on the transferred nanotubes. | 05-30-2013 |