Patent application number | Description | Published |
20090197390 | LOCK AND KEY STRUCTURE FOR THREE-DIMENTIONAL CHIP CONNECTION AND PROCESS THEREOF - A method positions a first wafer with respect to a second wafer such that key studs on the first wafer are fit (positioned) within lock openings in the second wafer. The key studs contact conductors within the second wafer. The edges of the first wafer are tacked to the edges of the second wafer. Then the wafers are pressed together and heat is applied to bond the wafers together. One feature of embodiments herein is that because the lock openings extend through an outer oxide (instead of a polyimide) the first wafer can be attached to the second wafer by using processing that occurs in the middle-of-the-line (MOL). | 08-06-2009 |
20090294989 | FORMATION OF VERTICAL DEVICES BY ELECTROPLATING - The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete metal contact pad located on the substrate surface, an inter-level dielectric (ILD) layer over both the discrete metal contact pad and the substrate, and a metal via structure extending through the ILD layer onto the discrete metal contact pad. Next, a vertical via is formed in the template structure, which extends through the ILD layer onto the discrete metal contact pad. A vertical conductive structure is then formed in the vertical via by electroplating, which is conducted by applying an electroplating current to the discrete metal contact pad through the metal via structure. Preferably, the template structure comprises multiple discrete metal contact pads, multiple metal via structures, and multiple vertical vias for formation of multiple vertical conductive structures. | 12-03-2009 |
20100196806 | STRUCTURES AND METHODS FOR LOW-K OR ULTRA LOW-K INTERLAYER DIELECTRIC PATTERN TRANSFER - The present invention relates to improved methods and structures for forming interconnect patterns in low-k or ultra low-k (i.e., having a dielectric constant ranging from about 1.5 to about 3.5) interlevel dielectric (ILD) materials. Specifically, reduced lithographic critical dimensions (CDs) (i.e., in comparison with target CDs) are initially used for forming a patterned resist layer with an increased thickness, which in turn allows use of a simple hard mask stack comprising a lower nitride mask layer and an upper oxide mask layer for subsequent pattern transfer. The hard mask stack is next patterned by a first reactive ion etching (RIE) process using an oxygen-containing chemistry to form hard mask openings with restored CDs that are substantially the same as the target CDs. The ILD materials are then patterned by a second RIE process using a nitrogen-containing chemistry to form the interconnect pattern with the target CDs. | 08-05-2010 |
20120008362 | Magnetic Spin Shift Register Memory - A method for forming a memory device includes forming a cavity having an inner surface with an undulating profile in a substrate, depositing a ferromagnetic material in the cavity, forming a reading element on the substrate proximate to a portion of the ferromagnetic material, and forming a writing element on the substrate proximate to a second portion of the ferromagnetic material. | 01-12-2012 |
20130005053 | Magnetic Spin Shift Register Memory - A method for forming a memory device includes forming a cavity having an inner surface with an undulating profile in a substrate, depositing a ferromagnetic material in the cavity, forming a reading element on the substrate proximate to a portion of the ferromagnetic material, and forming a writing element on the substrate proximate to a second portion of the ferromagnetic material. | 01-03-2013 |
Patent application number | Description | Published |
20090029543 | CLEANING PROCESS FOR MICROELECTRONIC DIELECTRIC AND METAL STRUCTURES - A method for cleaning a dielectric and metal structure within a microelectronic structure uses an oxygen containing plasma treatment, followed by an alcohol treatment, in turn followed by an aqueous organic acid treatment. Another method for cleaning a dielectric and metal structure within a microelectronic structure uses an aqueous surfactant treatment followed by an alcohol treatment and finally followed by an aqueous organic acid treatment. The former method may be used to clean a plasma etch residue from a dual damascene aperture. The second method may be used to clean a chemical mechanical polish planarizing residue from a dual damascene structure. The two methods may be used sequentially, absent any intervening or subsequent sputtering method, to provide a dual damascene structure within a microelectronic structure. | 01-29-2009 |
20090032978 | MICROELECTRONIC STRUCTURE INCLUDING DUAL DAMASCENE STRUCTURE AND HIGH CONTRAST ALIGNMENT MARK - A microelectronic structure, and in particular a semiconductor structure, includes a substrate and a dielectric layer located over the substrate. In addition at least one alignment mark is located interposed between the dielectric layer and the substrate. The at least one alignment mark comprises, or preferably consists essentially of, at least one substantially present element having an atomic number at least 5 greater than a highest atomic number substantially present element within materials surrounding the alignment mark Also included within the microelectronic structure is a dual damascene aperture located within the dielectric layer. The dual damascene aperture may be fabricated using, among other methods, a hybrid lithography method that uses direct write lithography and optical lithography, in conjunction with the at least one alignment mark and an electron beam as an alignment beam. | 02-05-2009 |
20090045530 | MICROELECTRONIC LITHOGRAPHIC ALIGNMENT USING HIGH CONTRAST ALIGNMENT MARK - A microelectronic structure, and in particular a semiconductor structure, includes a substrate that includes an alignment mark comprising a substantially present element that has an atomic number at least 5 greater than a highest atomic number substantially present element within the substrate. Alignment to the alignment mark may be effected using an electron beam as an alignment beam with respect to both a direct write exposure and a reticle filtered optical exposure of a mask layer (i.e., photoresist mask layer) located over the alignment mark and the substrate. The electron beam alignment beam may effectively penetrate through other layers, including conductor layers comprising elements having appropriately low atomic number, located interposed between the alignment mark and the mask layer. | 02-19-2009 |
20100048020 | Nanoscale Electrodes for Phase Change Memory Devices - A process for preparing a phase change memory semiconductor device comprising a (plurality of) nanoscale electrode(s) for alternately switching a chalcogenide phase change material from its high resistance (amorphous) state to its low resistance (crystalline) state, whereby a reduced amount of current is employed, and wherein the plurality of nanoscale electrodes, when present, have substantially the same dimensions. | 02-25-2010 |
Patent application number | Description | Published |
20100078770 | Lock and Key Through-Via Method for Wafer Level 3 D Integration and Structures Produced - A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art. | 04-01-2010 |
20110111560 | Lock and Key Through-Via Method for Wafer Level 3D Integration and Structures Produced Thereby - A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art. | 05-12-2011 |
20130029848 | LOW-LOSS SUPERCONDUCTING DEVICES - Low-loss superconducting devices and methods for fabricating low loss superconducting devices. For example, superconducting devices, such as superconducting resonator devices, are formed with a (200)-oriented texture titanium nitride (TiN) layer to provide high Q, low loss resonator structures particularly suitable for application to radio-frequency (RF) and/or microwave superconducting resonators, such as coplanar waveguide superconducting resonators. In one aspect, a method of forming a superconducting device includes foaming a silicon nitride (SiN) seed layer on a substrate, and forming a (200)-oriented texture titanium nitride (TiN) layer on the SiN seed layer. | 01-31-2013 |
20140264286 | SUSPENDED SUPERCONDUCTING QUBITS - A qubit system includes a substrate layer, a qubit circuit suspended above the substrate layer and fine structure disposed between the qubit circuit and the substrate layer. | 09-18-2014 |
20140264287 | REMOVAL OF SPURIOUS MICROWAVE MODES VIA FLIP-CHIP CROSSOVER - A coplanar waveguide device includes a coplanar waveguide structure disposed on a substrate, at least one qubit coupled to the coplanar waveguide structure and an add-on chip having a metallized trench, and disposed over the substrate. | 09-18-2014 |
20140274725 | CHIP MODE ISOLATION AND CROSS-TALK REDUCTION THROUGH BURIED METAL LAYERS AND THROUGH-VIAS - A method for fabricating a chip surface base includes preparing a first substrate, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias, preparing a second substrate, bonding the first and second substrates and exposing the metal fillings. A method for fabricating a chip surface base includes preparing a first and second substrate, depositing a metal on at least one of the first and second substrates, bonding the first and second substrates, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias and exposing the metal fillings. A chip surface base device includes a first substrate, a second substrate, a metal layer disposed between the first and second substrates and a plurality vias disposed on the first substrate. | 09-18-2014 |