Patent application number | Description | Published |
20140092728 | FAULTY CORE RECOVERY MECHANISMS FOR A THREE-DIMENSIONAL NETWORK ON A PROCESSOR ARRAY - Embodiments of the invention relate to faulty recovery mechanisms for a three-dimensional (3-D) network on a processor array. One embodiment comprises a multidimensional switch network for a processor array. The switch network comprises multiple switches for routing packets between multiple core circuits of the processor array. The switches are organized into multiple planes. The switch network further comprises a redundant plane including multiple redundant switches. Multiple data paths interconnect the switches. The redundant plane is used to facilitate full operation of the processor array in the event of one or more component failures. | 04-03-2014 |
20140095923 | FINAL FAULTY CORE RECOVERY MECHANISMS FOR A TWO-DIMENSIONAL NETWORK ON A PROCESSOR ARRAY - Embodiments of the invention relate to faulty recovery mechanisms for a two-dimensional (2-D) network on a processor array. One embodiment comprises a processor array including multiple processors core circuits, and a redundant routing system for routing packets between the core circuits. The redundant routing system comprises multiple switches, wherein each switch corresponds to one or more core circuits of the processor array. The redundant routing system further comprises multiple data paths interconnecting the switches, and a controller for selecting one or more data paths. Each selected data path is used to bypass at least one component failure of the processor array to facilitate full operation of the processor array. | 04-03-2014 |
20140180985 | MAPPING NEURAL DYNAMICS OF A NEURAL MODEL ON TO A COARSELY GRAINED LOOK-UP TABLE - Embodiments of the invention relate to mapping neural dynamics of a neural model on to a lookup table. One embodiment comprises defining a phase plane for a neural model. The phase plane represents neural dynamics of the neural model. The phase plane is coarsely sampled to obtain state transition information for multiple neuronal states. The state transition information is mapped on to a lookup table. | 06-26-2014 |
20140180988 | HARDWARE ARCHITECTURE FOR SIMULATING A NEURAL NETWORK OF NEURONS - Embodiments of the invention relate to a neural network system for simulating neurons of a neural model. One embodiment comprises a memory device that maintains neuronal states for multiple neurons, a lookup table that maintains state transition information for multiple neuronal states, and a controller unit that manages the memory device. The controller unit updates a neuronal state for each neuron based on incoming spike events targeting said neuron and state transition information corresponding to said neuronal state. | 06-26-2014 |
20140222740 | CONSOLIDATING MULTIPLE NEUROSYNAPTIC CORES INTO ONE MEMORY - Embodiments of the invention relate to a neural network system comprising a single memory block for multiple neurosynaptic core modules. One embodiment comprises a neural network system including a memory array that maintains information for multiple neurosynaptic core modules. Each neurosynaptic core module comprises multiple neurons. The neural network system further comprises at least one logic circuit. Each logic circuit receives neuronal firing events targeting a neurosynaptic core module of the neural network system, and said logic circuit integrates the firing events received based on information maintained in said memory for said neurosynaptic core module. | 08-07-2014 |
20140244971 | ARRAY OF PROCESSOR CORE CIRCUITS WITH REVERSIBLE TIERS - Embodiments of the invention relate to an array of processor core circuits with reversible tiers. One embodiment comprises multiple tiers of core circuits and multiple switches for routing packets between the core circuits. Each tier comprises at least one core circuit. Each switch comprises multiple router channels for routing packets in different directions relative to the switch, and at least one routing circuit configured for reversing a logical direction of at least one router channel. | 08-28-2014 |
20150227558 | MAPPING NEURAL DYNAMICS OF A NEURAL MODEL ON TO A COARSELY GRAINED LOOK-UP TABLE - Embodiments of the invention relate to mapping neural dynamics of a neural model on to a lookup table. One embodiment comprises defining a phase plane for a neural model. The phase plane represents neural dynamics of the neural model. The phase plane is coarsely sampled to obtain state transition information for multiple neuronal states. The state transition information is mapped on to a lookup table. | 08-13-2015 |
20150254551 | MULTIPLEXING PHYSICAL NEURONS TO OPTIMIZE POWER AND AREA - Embodiments of the invention relate to a multiplexed neural core circuit. One embodiment comprises a neural core circuit including a memory device that maintains neuronal attributes for multiple neurons. The memory device has multiple entries. Each entry maintains neuronal attributes for a corresponding neuron. The core circuit further comprises a controller for managing the memory device and processing neuronal firing events targeting each neuron. The controller multiplexes computation and control logic for the neurons. In response to neuronal firing events targeting one of the neurons, the controller retrieves neuronal attributes for the target neuron from a corresponding entry of the memory device, and integrates the firing events based on the retrieved neuronal attributes to generate a firing event for the target neuron. | 09-10-2015 |