Patent application number | Description | Published |
20090141533 | METAL GATE COMPATIBLE ELECTRICAL ANTIFUSE - A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor portion and a metal gate portion, which is preferably performed concurrently with formation of at least one metal gate stack. In one embodiment, the size of the semiconductor portion is reduced and a metal semiconductor alloy portion is formed on the semiconductor portion by metallization. In a first electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the metal semiconductor alloy portion and the metal gate portion. In another embodiment, two disjoined metal semiconductor alloy portions are formed on the semiconductor portion. In a second electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the two previously disjoined metal semiconductor alloy portions. | 06-04-2009 |
20100327399 | ELECTRICALLY PROGRAMMABLE FUSE USING ANISOMETRIC CONTACTS AND FABRICATION METHOD - An electrically programmable fuse that includes an anode contact region and a cathode contact region are formed of a polysilicon layer having a silicide layer formed thereon, and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, and a plurality of anisometric contacts formed on the silicide layer of the cathode contact region or on both the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively. | 12-30-2010 |
20120012977 | SECURE ANTI-FUSE WITH LOW VOLTAGE PROGRAMMING THROUGH LOCALIZED DIFFUSION HEATING - An antifuse is provided having a unitary monocrystalline semiconductor body including first and second semiconductor regions each having the same first conductivity type, and a third semiconductor region between the first and second semiconductor regions which has a second conductivity type opposite from the first conductivity type. An anode and a cathode can be electrically connected with the first semiconductor region. A conductive region including a metal, a conductive compound of a metal or an alloy of a metal can contact the first semiconductor region and extend between the cathode and the anode. The antifuse can further include a contact electrically connected with the second semiconductor region. In this way, the antifuse can be configured such that the application of a programming voltage between the anode and the cathode heats the first semiconductor region sufficiently to reach a temperature which drives a dopant outwardly therefrom, causing an edge of the first semiconductor region to move closer to an adjacent edge of the second semiconductor region, thus permanently reducing electrical resistance between the first and second semiconductor regions by one or more orders of magnitude. | 01-19-2012 |
20120171857 | ELECTRICALLY PROGRAMMABLE FUSE USING ANISOMETRIC CONTACTS AND FABRICATION METHOD - A fabrication method for fabricating an electrically programmable fuse method includes depositing a polysilicon layer on a substrate, patterning an anode contact region, a cathode contact region and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, depositing a silicide layer on the polysilicon layer, and forming a plurality of anisometric contacts on the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively. | 07-05-2012 |
20130063202 | SECURE ANTI-FUSE WITH LOW VOLTAGE PROGRAMMING THROUGH LOCALIZED DIFFUSION HEATING - An antifuse has first and second semiconductor regions having one conductivity type and a third semiconductor region therebetween having an opposite conductivity type. A conductive region contacting the first region has a long dimension in a second direction transverse to the direction of a long dimension of a gate. An antifuse anode is spaced apart from the first region in the second direction and a contact is connected with the second region. Applying a programming voltage between the anode and the contact with gate bias sufficient to fully turn on field effect transistor operation of the antifuse heats the first region to drive a dopant outwardly, causing an edge of the first region to move closer to an edge of the second region and reduce electrical resistance between the first and second regions by an one or more orders of magnitude. | 03-14-2013 |
20130133031 | Retention Based Intrinsic Fingerprint Identification Featuring A Fuzzy Algorithm and a Dynamic Key - A random intrinsic chip ID generation employs a retention fail signature. A 1 | 05-23-2013 |
20130285694 | THROUGH-SILICON-VIA WITH SACRIFICIAL DIELECTRIC LINE - A TSV structure, method of making the TSV structure and methods of testing the TSV structure. The structure including: a trench extending from a top surface of a semiconductor substrate to a bottom surface of the semiconductor substrate, the trench surrounding a core region of the semiconductor substrate; a dielectric liner on all sidewalls of the trench; and an electrical conductor filling all remaining space in the trench, the dielectric liner electrically isolating the electrical conductor from the semiconductor substrate and from the core region. | 10-31-2013 |
20140145750 | CIRCUITS FOR SELF-RECONFIGURATION OR INTRINSIC FUNCTIONAL CHANGES OF CHIPS BEFORE VS. AFTER STACKING - A method and system for testing one or more semiconductor structures, for example, chips or wafers, in a three-dimensional stack. The method and system includes controlling a logic signal of a first circuit in a first chip or wafer connected to a supply voltage to indicate a first state during pre-assembly testing of the first chip or wafer. The method and system further includes controlling the logic signal to indicate a second state when the first circuit is connected to a second circuit of a second chip or wafer resulting in a combined circuit. The combined circuit is in a three-dimensional chip or wafer stack during post-assembly testing of the three-dimensional chip or wafer stack. | 05-29-2014 |
Patent application number | Description | Published |
20090267179 | SYSTEM FOR POWER PERFORMANCE OPTIMIZATION OF MULTICORE PROCESSOR CHIP - A system in one embodiment includes a multiprocessor chip comprising a plurality of cores; a plurality of power circuits, each power circuit being coupled to one of the cores; and an electrically programmable fuse in each power circuit. Each electrically programmable fuse further comprises a first electrode coupled to the associated power circuit; a second electrode coupled to the associated power circuit; a first pad coupled to the first electrode; a second pad coupled to the second electrode; and an electrically conductive material extending between the first and second electrodes and forming part of the associated power circuit, the electrically conductive material being characterized as tending to electromigrate from one of the electrodes to the other electrode under an applied electrical current passing between the electrodes, wherein the electromigration increases an overall resistance of the power circuit. | 10-29-2009 |
20090283840 | METAL GATE INTEGRATION STRUCTURE AND METHOD INCLUDING METAL FUSE, ANTI-FUSE AND/OR RESISTOR - A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode. | 11-19-2009 |
20130307159 | PHYSICAL DESIGN SYMMETRY AND INTEGRATED CIRCUITS ENABLING THREEDIMENTIONAL (3D) YIELD OPTIMIZATION FOR WAFER TO WAFER STACKING - One of the wafers in a semiconductor wafer to wafer stack can be rotated a predefined number of positions, relative to a previous wafer in the stack, and bonded in the position in which the maximum number of good die are aligned. An adjustment circuit on each die reroutes signals received from a pad that has been relocated due to rotation. A communication channel formed from a pair of pads that are interconnected by a Through Substrate Vias can be placed in each die and can convey selected information from one die to the next. A code representative of the position orientation of each die can be recorded in a Programmable Read Only Memory located on each die, or may be down loaded from a remote source. Any additional wafer may be stacked serially, and each one may be rotated relative to the wafer that precedes it in the stack. | 11-21-2013 |
Patent application number | Description | Published |
20080261567 | Mobile telephony device having a print request dedicated key for transmitting digital images to a printing system - A mobile telephony device is provided having a print request dedicated key, a digital image acquiring assembly for acquiring at least one digital image, and a processor in operative communication with the print request dedicated key for initiating printing of the at least one digital image in response to selection of the print request dedicated key by a user of the mobile telephony device. The processor includes a memory module configured for storing digital images acquired by the digital image acquiring assembly. The processor further includes a transmission module programmed with transmission instructions for transmitting the at least one digital image in response to the selection of the print request dedicated key. The processor further includes a payment module programmed with payment-related information capable of being transmitted by the transmission module for use in effecting payment to a service provider or an order fulfillment location for printing the at least one digital image. | 10-23-2008 |
20080288520 | Node Processing of Variable Information Print Jobs - Embodiments herein begin by receiving user input. The embodiments herein create a fixed data file and a text string based on the user input using a process manager located within a system. The embodiments herein also supply the fixed data file and the text string from the process manager to at least one node within the system. The system comprises a plurality of such nodes. The node executes the text string to add variable data to the fixed data and create a variable information print file. More specifically, the node retrieves the variable data from a database within the system. Then, the method can print the variable information print file. | 11-20-2008 |
20100214590 | METHOD FOR PROTECTING CONTENT OF A FAX CONFIRMATION SHEET - What is provided are a system, method, and computer program product for protecting information displayed on a fax confirmation page. Several embodiments are provided. In one embodiment, for example, a Gaussian kernel is used to blur the digitized image to be printed on the confirmation page. In one method, a large enough blur kernel is selected so that text of a certain size will be rendered illegible. A method is also provided wherein a copy of the first page of the faxed document used to provide the content to be displayed on the confirmation page of the faxed document is stored on a storage device. A character sequence which references the stored original content on the storage media is printed on the confirmation page. A new confirmation page can be reconstructed and printed if it is desirable to have the altered content made visibly legible. Various other embodiments are disclosed. | 08-26-2010 |
20110023740 | Offset Printing Process Using Light Controlled Wettability - A lithographic printing method including exposing an imaging surface layer of a printing plate to a first expose source to render the surface layer uniformly hydrophilic; the surface layer comprising a compound having reversible light controlled wettability whereby the surface layer is reversibly hydrophilic and hydrophobic. The surface layer is disposed over a variable image portion of the printing plate imaging surface or disposed over substantially all of the printing plate imaging surface. The surface is exposed to a second expose source to render image areas of the surface layer hydrophobic. Polar liquid attracts to non-image hydrophilic areas. Hydrophobic liquid colorant attracts to hydrophobic image areas. The surface layer is contacted an offset receiving member and the image is transferred to an image receiving substrate. | 02-03-2011 |
20110026050 | Laser Printing Process Using Light Controlled Wettability - A light controlled laser imaging method includes exposing a surface layer of an imaging member substrate to a first expose source to render the surface layer uniformly hydrophilic, wherein the surface layer comprises a compound having reversible light controlled wettability whereby the surface layer is reversibly hydrophilic and hydrophobic; exposing the surface layer to a second expose source in an image-wise fashion to render image areas of the surface layer hydrophobic; exposing the surface layer to a polar liquid wherein the polar liquid attracts to non-image hydrophilic areas; exposing the surface layer to a hydrophobic liquid colorant wherein the hydrophobic liquid colorant attracts to hydrophobic image areas; contacting the surface layer with an image receiving substrate to transfer the image thereto; fixing the image; and optionally, treating the surface layer to remove residual hydrophobic liquid colorant. | 02-03-2011 |