Patent application number | Description | Published |
20080210927 | Buffer architecture formed on a semiconductor wafer - In one embodiment, the present invention includes an apparatus for forming a transistor that includes a silicon (Si) substrate, a dislocation filtering buffer formed over the Si substrate having a first buffer layer including gallium arsenide (GaAs) nucleation and buffer layers and a second buffer layer including a graded indium aluminium arsenide (InAlAs) buffer layer, a lower barrier layer formed on the second buffer layer formed of InAlAs, and a strained quantum well (QW) layer formed on the lower barrier layer of indium gallium arsenide (InGaAs). Other embodiments are described and claimed. | 09-04-2008 |
20080237672 | High density memory - In one embodiment of the invention, a method of forming a semiconductor device includes forming a dynamic random access memory using spacer-defined lithography. | 10-02-2008 |
20080303116 | SEMICONDUCTOR ON INSULATOR APPARATUS - A method and apparatus for producing a relatively thin, relatively uniform semiconductor layer which has improved carrier mobility. In an embodiment, a lattice-matched insulator layer is formed on a semiconductor substrate, and a lattice-matched semiconductor layer is formed on the insulator layer to form a relatively thin, relatively uniform semiconductor on insulator apparatus. In embodiments of the method and apparatus, energy band characteristics may be used to facilitate the extraction of the well-region minority carriers. | 12-11-2008 |
20090085082 | CONTROLLED INTERMIXING OF HFO2 AND ZRO2 DIELECTRICS ENABLING HIGHER DIELECTRIC CONSTANT AND REDUCED GATE LEAKAGE - Controlled deposition of HfO | 04-02-2009 |
20090315076 | TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER - Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material. | 12-24-2009 |
20100038717 | Semiconductor on Insulator Apparatus - A method and apparatus for producing a relatively thin, relatively uniform semiconductor layer which has improved carrier mobility. In an embodiment, a lattice-matched insulator layer is formed on a semiconductor substrate, and a lattice-matched semiconductor layer is formed on the insulator layer to form a relatively thin, relatively uniform semiconductor on insulator apparatus. In embodiments of the method and apparatus, energy band characteristics may be used to facilitate the extraction of the well-region minority carriers. | 02-18-2010 |
20100044754 | STRAINED TRANSISTOR INTEGRATION FOR CMOS - Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area. | 02-25-2010 |
20100164102 | Isolated germanium nanowire on silicon fin - The present invention describes a method of and an apparatus for providing a wafer, the wafer including Silicon; etching trenches in the wafer to form Silicon fins; filling Silicon Oxide in the trenches; planarizing the Silicon Oxide; recessing the Silicon Oxide to a first thickness to form exposed Silicon pedestals from the Silicon fins; depositing SiGe over the exposed Silicon pedestal; recessing the Silicon Oxide to a second thickness; undercutting the exposed Silicon pedestals to form necked-in Silicon pedestals; oxidizing thermally and annealing the SiGe; and forming Germanium nanowires. | 07-01-2010 |
20100230658 | Apparatus and methods for improving parallel conduction in a quantum well device - Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed. | 09-16-2010 |
20100285279 | METHODS OF FORMING NANODOTS USING SPACER PATTERNING TECHNIQUES AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a first block on a nanodot material, forming a first spacer on the first block, removing the first block to form a free standing spacer, removing exposed portions of the nanodot material and then the free standing spacer to form nanowires, forming a second block at an angle to a length of the nanowires, forming a second spacer on the second block, forming a second free standing spacer on the nanowires by removing the second block, and removing exposed portions of the nanowires and then the second free standing spacer to form an ordered array of nanodots. | 11-11-2010 |
20110018031 | TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER - Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material. | 01-27-2011 |
20110039377 | Semiconductor on Insulator - A method and apparatus for producing a relatively thin, relatively uniform semiconductor layer which has improved carrier mobility. In an embodiment, a lattice-matched insulator layer is formed on a semiconductor substrate, and a lattice-matched semiconductor layer is formed on the insulator layer to form a relatively thin, relatively uniform semiconductor on insulator apparatus. In embodiments of the method and apparatus, energy band characteristics may be used to facilitate the extraction of the well-region minority carriers. | 02-17-2011 |
20110186912 | TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER - Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material. | 08-04-2011 |
20120032146 | APPARATUS AND METHODS FOR IMPROVING PARALLEL CONDUCTION IN A QUANTUM WELL DEVICE - Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed. | 02-09-2012 |
20120074386 | Non-planar quantum well device having interfacial layer and method of forming same - Techniques are disclosed for forming a non-planar quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), and a quantum well layer. A fin structure is formed in the quantum well structure, and an interfacial layer provided over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure. | 03-29-2012 |
20120326123 | APPARATUS AND METHODS FOR IMPROVING PARALLEL CONDUCTION IN A QUANTUM WELL DEVICE - Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed. | 12-27-2012 |
20130153965 | STRAINED TRANSISTOR INTEGRATION FOR CMOS - Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area. | 06-20-2013 |
20130270512 | CMOS IMPLEMENTATION OF GERMANIUM AND III-V NANOWIRES AND NANORIBBONS IN GATE-ALL-AROUND ARCHITECTURE - Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area. | 10-17-2013 |
20130271208 | GROUP III-N TRANSISTORS FOR SYSTEM ON CHIP (SOC) ARCHITECTURE INTEGRATING POWER MANAGEMENT AND RADIO FREQUENCY CIRCUITS - System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) that is capable of achieving high F | 10-17-2013 |
20130277683 | NON-PLANAR III-N TRANSISTOR - Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls includes a channel region with a first crystalline semiconductor layer disposed over the first and second sidewalls. The first crystalline semiconductor layer is to provide a two dimensional electron gas (2DEG) within the channel region. A gate structure is disposed over the first crystalline semiconductor layer along at least the second sidewall to modulate the 2DEG. First and second sidewalls of the non-planar polar crystalline semiconductor body may have differing polarity, with the channel proximate to a first of the sidewalls. The gate structure may be along a second of the sidewalls to gate a back barrier. The polar crystalline semiconductor body may be a group III-nitride formed on a silicon substrate with the (10 | 10-24-2013 |
20130279145 | GROUP III-N NANOWIRE TRANSISTORS - A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions. | 10-24-2013 |
20130307513 | HIGH VOLTAGE FIELD EFFECT TRANSISTORS - Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions. | 11-21-2013 |
20130313520 | APPARATUS AND METHODS FOR IMPROVING PARALLEL CONDUCTION IN A QUANTUM WELL DEVICE - Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed. | 11-28-2013 |