Patent application number | Description | Published |
20090321740 | TFT-LCD ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - A TFT-LCD array substrate and a manufacturing method thereof. The array substrate comprises a gate line, a data line, and a pixel electrode, and the pixel electrode is disposed in a pixel region defined by the intersection between the gate line and the data line. In the pixel region, a partition groove for forming a pixel electrode pattern is provided at the periphery of the pixel electrode. This structure is helpful to form a pixel electrode pattern by a lift-off process, which significantly reduces the production cost and improves the production yield. | 12-31-2009 |
20100012945 | METHOD OF FORMING PHOTORESIST BURR EDGE AND METHOD OF MANUFACTURING ARRAY SUBSTRATE - A method of forming a photoresist burr edge and a method of manufacturing an array substrate are provided in the present invention. The method of manufacturing an array substrate comprises: forming a gate line and a gate electrode on a substrate; forming a data line, a source electrode, a drain electrode and a TFT channel region without removing the photoresist on the data line, the source electrode and the drain electrode; depositing a passivation layer; removing the remained photoresist and the passivation layer thereon by a lifting-off process; applying a photoresist layer; forming a photoresist burr edge of peak shape; depositing a transparent conductive film; forming a pixel electrode by a lifting-off process, wherein the pixel electrode is directly connected with the drain electrode. | 01-21-2010 |
20110068341 | TFT-LCD ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - An embodiment of the invention relates to a TFT-LCD array substrate comprising a substrate, a gate line and a data line formed on the substrate, a pixel electrode and a thin film transistor formed in a pixel region defined by the gate line and the data line, wherein the thin film transistor comprises a gate electrode, a source electrode, and a transparent drain electrode, and the transparent drain electrode is electrically connected with the pixel electrode. | 03-24-2011 |
20130169903 | TFT-LCD ARRAY SUBSTRATE - A Thin Film Transistor-Liquid Crystal Display (TFT-LCD) array substrate is presented which includes a gate line, a data line, and a pixel electrode. The pixel electrode is disposed in a pixel region defined by the intersection between the gate line and the data line. In the pixel region, a partition groove for forming a pixel electrode pattern is provided at the periphery of the pixel electrode. | 07-04-2013 |
20140097437 | THIN FILM TRANSISTOR, DISPLAY DEVICE AND MANUFACTURING THEREOF, DISPLAY APPARATUS - A thin-film transistor (TFT) comprises a gate electrode, a gate insulating layer, a source electrode and a drain electrode which are formed on a base substrate, the source electrode and the drain electrode are disposed on different layers and isolated from each other through a semiconductor connecting section made of an oxide semiconductor material; a position of the semiconductor connecting section corresponds to a position of the gate electrode; and at least one part of the source electrode and at least one part of the drain electrode overlap each other at a position corresponding to the semiconductor connecting section. A display device comprising the TFT and a display device comprising the display device are also disclosed. | 04-10-2014 |
20140220747 | TFT-LCD ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - An embodiment of the invention relates to a TFT-LCD array substrate comprising a substrate, a gate line and a data line formed on the substrate, a pixel electrode and a thin film transistor formed in a pixel region defined by the gate line and the data line, wherein the thin film transistor comprises a gate electrode, a source electrode, and a transparent drain electrode, and the transparent drain electrode is electrically connected with the pixel electrode. | 08-07-2014 |
Patent application number | Description | Published |
20090302905 | METHOD AND APPARATUS FOR ON-CHIP PHASE ERROR MEASUREMENT TO DETERMINE JITTER IN PHASE-LOCKED LOOPS - An apparatus includes a phase-locked loop (PLL) circuit including a phase-frequency detector configured to output phase error signals. A phase error monitor circuit is configured to determine instantaneous peak phase error by logically combining the phase error signals and comparing pulse widths of the logically combined phase error signals to a programmable delay time at each reference clock cycle to determine instantaneous phase error change. A storage element is configured to store the instantaneous phase error change. | 12-10-2009 |
20090302906 | METHOD AND APPARATUS FOR ON-CHIP PHASE ERROR MEASUREMENT TO DETERMINE JITTER IN PHASE-LOCKED LOOPS - An apparatus includes a phase-locked loop (PLL) circuit including a phase-frequency detector configured to output phase error signals. A phase error monitor circuit is configured to determine instantaneous peak phase error by logically combining the phase error signals and comparing pulse widths of the logically combined phase error signals to a programmable delay time at each reference clock cycle to determine instantaneous phase error change. A storage element is configured to store the instantaneous phase error change. | 12-10-2009 |
20100225361 | FREQUENCY DIVIDER, FREQUENCY SYNTHESIZER AND APPLICATION CIRCUIT - A frequency divider includes a prescaler and multiple modulus dividers commonly coupled to the prescaler. The prescaler generates intermediate frequency signals having a same phase difference with respect to one another in response to an oscillation frequency signal. The prescaler operates at a first frequency. The modulus dividers respectively divide the intermediate frequency signals with respective ratio to provide a plurality of division frequency signals in response to a control signal. The modulus dividers operate at a second frequency less than the first frequency. | 09-09-2010 |
20100302885 | DELAY LOCKED LOOP AND METHOD AND ELECTRONIC DEVICE INCLUDING THE SAME - A delay locked loop and method and electronic device including the delay locked loop are provided. In one embodiment, the delay locked loop includes a first delay locked loop and a second delay locked loop. The first delay locked loop receives a data signal and a plurality of first clock signals, generates a plurality of second clock signals based on interpolation on the plurality of first clock signals, selects and outputs one of the second clock signals from among the plurality of second clock signals based on a locking operation on the plurality of second clock signals and the data signal, and generates a plurality of phase resolution control signals. The second delay locked loop receives the data signal, the selected second clock signal, and the plurality of phase resolution control signals, generates a plurality of third clock signals having variable phase resolution based on the selected second clock signal and at least one of the plurality of phase resolution control signals, and performs a locking operation on the plurality of third clock signals and the data signal. | 12-02-2010 |
20110002181 | Delay locked loop using hybrid fir filtering technique and semiconductor memory device having the same - Example embodiments are directed to a delay locked loop (DLL) circuit based on a hybrid finite impulse response (FIR) filtering technique, and a semiconductor memory device including the DLL circuit. The DLL circuit includes a frequency divider and a self-referenced multiphase generator (SRMG) and allows a Sigma-Delta (ΣΔ) modulator to operate at a low frequency without generating false lock and glitch noise. | 01-06-2011 |
20120280731 | PHASE-LOCKED-LOOP CIRCUIT INCLUDING DIGITALLY-CONTROLLED OSCILLATOR - A phase-locked-loop (PLL) circuit is provided. The PLL circuit includes a phase/frequency detector, a digital filter, a digital low pass filter (LPF), a digitally controlled oscillator (DCO), and a frequency divider. The digital LPF performs a low-pass-filtering on least significant bits of first digital data in a digital mode and generates filtered second digital data. The DCO performs a digital-to-analog conversion on the second digital data and most significant bits of the first digital data to generate a first signal, generates an oscillation control signal based on the first signal, and generates an output clock signal oscillating in response to the oscillation control signal. | 11-08-2012 |
20130243043 | TRANSMITTER AND RECEIVER FOR REDUCING POWER CONSUMPTION IN FM-UWB COMMUNICATION SYSTEM - A transmitter and a receiver for reducing power consumption in a frequency modulation-ultra-wideband (FM-UWB) communication system are provided. The transmitter includes a detector configured to generate a pulse signal when an edge of a digital signal is detected. The transmitter further includes a first modulator configured to modulate the digital signal into a first modulation signal based on a value of the digital signal. The transmitter further includes a second modulator configured to modulate the first modulation signal into a second modulation signal based on a frequency of the first modulation signal when the pulse signal is generated. | 09-19-2013 |
20140050250 | APPARATUS AND METHOD FOR GENERATING GAUSSIAN PULSE AND ULTRA WIDEBAND COMMUNICATION APPARATUS FOR GENERATING GAUSSIAN PULSE - A pulse generation apparatus includes a delay pulse generator configured to generate a plurality of delay pulses, an amplitude modulator configured to modulate amplitudes of the plurality of delay pulses, and a Gaussian pulse generator configured to generate a Gaussian pulse based on the amplitude-modulated delay pulses. | 02-20-2014 |
20140050252 | APPARATUS AND METHOD FOR ULTRA WIDEBAND COMMUNICATION USING DUAL BAND PASS FILTER - An apparatus and method for ultra wideband (UWB) communication, using a dual band pass filter (BPF) is disclosed. The UWB communication apparatus may include a first BPF performing a first band pass filtering with respect to a UWB signal, a second BPF that has a center frequency differing from a center frequency of the first BPF, and performs a second band pass filtering with respect to the UWB signal, a first envelope detector that detects a size of a first signal filtered in the first BPF, a second envelope detector that detects a size of a second signal filtered in the second BPF, and a demodulator that demodulates a UWB signal, using the size of the first signal and the size of the second signal. | 02-20-2014 |