Patent application number | Description | Published |
20100304542 | ENHANCED ETCH STOP CAPABILITY DURING PATTERNING OF SILICON NITRIDE INCLUDING LAYER STACKS BY PROVIDING A CHEMICALLY FORMED OXIDE LAYER DURING SEMICONDUCTOR PROCESSING - A gate electrode structure may be formed on the basis of a silicon nitride cap material in combination with a very thin yet uniform silicon oxide based etch stop material, which may be formed on the basis of a chemically driven oxidation process. Due to the reduced thickness, a pronounced material erosion, for instance, during a wet chemical cleaning process after gate patterning, may be avoided, thereby not unduly affecting the further processing, for instance with respect to forming an embedded strain-inducing semiconductor alloy, while nevertheless providing the desired etch stop capabilities during removing the silicon nitride cap material. | 12-02-2010 |
20100327373 | UNIFORM HIGH-K METAL GATE STACKS BY ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A METAL SPECIES PRIOR TO GATE PATTERNING - Sophisticated gate electrode structures for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material and subsequently a common gate layer stack is deposited and subsequently patterned. | 12-30-2010 |
20100330790 | TECHNIQUE FOR EXPOSING A PLACEHOLDER MATERIAL IN A REPLACEMENT GATE APPROACH BY MODIFYING A REMOVAL RATE OF STRESSED DIELECTRIC OVERLAYERS - In a replacement gate approach, the sacrificial gate material is exposed on the basis of enhanced process uniformity, for instance during a wet chemical etch step or a CMP process, by forming a modified portion in the interlayer dielectric material by ion implantation. Consequently, the damaged portion may be removed with an increased removal rate while avoiding the creation of polymer contaminants when applying an etch process or avoiding over-polish time when applying a CMP process. | 12-30-2010 |
20110049585 | MAINTAINING INTEGRITY OF A HIGH-K GATE STACK BY PASSIVATION USING AN OXYGEN PLASMA - In semiconductor devices, integrity of a titanium nitride material may be increased by exposing the material to an oxygen plasma after forming a thin silicon nitride-based material. The oxygen plasma may result in an additional passivation of any minute surface portions which may not be appropriately covered by the silicon nitride-based material. Consequently, efficient cleaning recipes, such as cleaning processes based on SPM, may be performed after the additional passivation without undue material loss of the titanium nitride material. In this manner, sophisticated high-k metal gate stacks may be formed with a very thin protective liner material on the basis of efficient cleaning processes without unduly contributing to a pronounced yield loss in an early manufacturing stage. | 03-03-2011 |
20110189831 | REDUCING CONTAMINATION IN A PROCESS FLOW OF FORMING A CHANNEL SEMICONDUCTOR ALLOY IN A SEMICONDUCTOR DEVICE - In sophisticated approaches for forming high-k metal gate electrode structures in an early manufacturing stage, a threshold adjusting semiconductor alloy may be deposited on the basis of a selective epitaxial growth process without affecting the back side of the substrates. Consequently, any negative effects, such as contamination of substrates and process tools, reduced surface quality of the back side and the like, may be suppressed or reduced by providing a mask material and preserving the material at least during the selective epitaxial growth process. | 08-04-2011 |
20120086056 | Superior Integrity of a High-K Gate Stack by Forming a Controlled Undercut on the Basis of a Wet Chemistry - In sophisticated semiconductor devices, the encapsulation of sensitive gate materials, such as a high-k dielectric material and a metal-containing electrode material, which are provided in an early manufacturing stage may be achieved by forming an undercut gate configuration. To this end, a wet chemical etch sequence is applied after the basic patterning of the gate layer stack, wherein at least ozone-based and hydrofluoric acid-based process steps are performed in an alternating manner, thereby achieving a substantially self-limiting removal behavior. | 04-12-2012 |
20120282764 | TECHNIQUE FOR EXPOSING A PLACEHOLDER MATERIAL IN A REPLACEMENT GATE APPROACH BY MODIFYING A REMOVAL RATE OF STRESSED DIELECTRIC OVERLAYERS - In a replacement gate approach, the sacrificial gate material is exposed on the basis of enhanced process uniformity, for instance during a wet chemical etch step or a CMP process, by forming a modified portion in the interlayer dielectric material by ion implantation. Consequently, the damaged portion may be removed with an increased removal rate while avoiding the creation of polymer contaminants when applying an etch process or avoiding over-polish time when applying a CMP process. | 11-08-2012 |
20130122716 | Methods of Controlling the Etching of Silicon Nitride Relative to Silicon Dioxide - Disclosed herein are methods of controlling the etching of a layer of silicon nitride relative to a layer of silicon dioxide. In one illustrative example, the method includes providing an etch bath that is comprised of an existing etchant adapted to selectively etch silicon nitride relative to silicon dioxide, performing an etching process in the etch bath using the existing etchant to selectively remove a silicon nitride material positioned above a silicon dioxide material on a plurality of semiconducting substrates, determining an amount of the existing etchant to be removed based upon a per substrate silicon loading of the etch bath by virtue of etching the plurality of substrates in the etch bath and determining an amount of new etchant to be added to the etch bath based upon a per substrate silicon loading of the etch bath by virtue of etching the plurality of substrates in the etch bath. | 05-16-2013 |
20130126984 | Patterning of Sensitive Metal-Containing Layers With Superior Mask Material Adhesion by Providing a Modified Surface Layer - When patterning metal-containing material layers, such as titanium nitride, in critical manufacturing stages, for instance upon forming sophisticated high-k metal gate electrode structures or providing hard mask materials for patterning a metallization system, the surface adhesion of a resist material on the titanium nitride material may be improved by applying a controlled oxidation process. | 05-23-2013 |
20130203244 | METHODS FOR PFET FABRICATION USING APM SOLUTIONS - A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing an integrated circuit comprising a p-type field effect transistor (pFET), recessing a surface region of the pFET using an ammonia-hydrogen peroxide-water (APM) solution to form a recessed pFET surface region, and depositing a silicon-based material channel on the recessed pFET surface region. | 08-08-2013 |
20130203245 | METHODS FOR PFET FABRICATION USING APM SOLUTIONS - A method for fabricating an integrated circuit from a semiconductor substrate having formed thereon over a first portion of the semiconductor substrate a hard mask layer and having formed thereon over a second portion of the semiconductor substrate an oxide layer. The first portion and the second portion are electrically isolated by a shallow trench isolation feature. The method includes removing the oxide layer from over the second portion and recessing the surface region of the second portion by applying an ammonia-hydrogen peroxide-water (APM) solution to form a recessed surface region. The APM solution is provided in a concentration of ammonium to hydrogen peroxide ranging from about 1:1 to about 1:0.001 and in a concentration of ammonium to water ranging from about 1:1 to about 1:20. The method further includes epitaxially growing a silicon-germanium (SiGe) layer on the recessed surface region. | 08-08-2013 |
20130299874 | TMAH RECESS FOR SILICON GERMANIUM IN POSITIVE CHANNEL REGION FOR CMOS DEVICE - CMOS devices are enhanced by forming a recess in the positive channel for depositing SiGe. Embodiments include providing a positive channel region and a negative channel region in a silicon substrate for a CMOS device, with an STI region therebetween; removing a native oxide from above the positive channel region to expose a silicon substrate; forming a recess in the silicon substrate in the positive channel region adjacent the STI region; and depositing SiGe in the recess in the positive channel region, where an upper surface of the SiGe is substantially level with an upper surface of the negative channel region. | 11-14-2013 |
20140113455 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A WET ETCH PROCESS FOR REMOVING SILICON NITRIDE - A method disclosed herein includes providing a semiconductor structure comprising a transistor, the transistor comprising a gate electrode and a silicon nitride sidewall spacer formed at the gate electrode. A wet etch process is performed. The wet etch process removes at least a portion of the silicon nitride sidewall spacer. The wet etch process comprises applying an etchant comprising at least one of hydrofluoric acid and phosphoric acid. | 04-24-2014 |
20150024578 | METHODS FOR ETCHING DIELECTRIC MATERIALS IN THE FABRICATION OF INTEGRATED CIRCUITS - Methods for etching dielectric materials in the fabrication of integrated circuits are disclosed herein. In one exemplary embodiment, a method for fabricating an integrated circuit includes forming a layer of a first dielectric material over a gate electrode structure formed on a semiconductor substrate. The gate electrode structure includes a horizontal top surface and sidewall vertical surfaces adjacent to the horizontal top surface. The method further includes forming a layer of a second dielectric material over the layer of the first dielectric material. The first dielectric material is different than the second dielectric material. Still further, the method includes applying an etchant to the second material that fully removes the second material from the sidewall vertical surfaces while only partially removing the second material from the horizontal top surface and while substantially not removing any of the layer of the first dielectric material. | 01-22-2015 |
20150137270 | SUPERIOR INTEGRITY OF A HIGH-K GATE STACK BY FORMING A CONTROLLED UNDERCUT ON THE BASIS OF A WET CHEMISTRY - A transistor device includes a gate electrode structure. The gate electrode structure includes a high-k gate insulation layer, a metal-containing first electrode material positioned above the high-k gate insulation layer, and a second electrode material positioned above the metal-containing first electrode material. The high-k gate insulation layer has a length that is less than a length of the second electrode material. | 05-21-2015 |
20150235906 | METHODS FOR ETCHING DIELECTRIC MATERIALS IN THE FABRICATION OF INTEGRATED CIRCUITS - Methods for etching dielectric materials in the fabrication of integrated circuits are disclosed herein. In one exemplary embodiment, a method for fabricating an integrated circuit includes forming a layer of a first dielectric material over a gate electrode structure formed on a semiconductor substrate. The gate electrode structure includes a horizontal top surface and sidewall vertical surfaces adjacent to the horizontal top surface. The method further includes forming a layer of a second dielectric material over the layer of the first dielectric material. The first dielectric material is different than the second dielectric material. Still further, the method includes applying an etchant to the second material that fully removes the second material from the sidewall vertical surfaces while only partially removing the second material from the horizontal top surface and while substantially not removing any of the layer of the first dielectric material. | 08-20-2015 |
Patent application number | Description | Published |
20100247631 | PREPARATIONS FOR THE EXTERNAL APPLICATION OF ANTISEPTIC AGENTS AND/OR AGENTS PROMOTING THE HEALING OF WOUNDS - The present invention relates to liposomal pharmaceutical preparations which include active agents such as antiseptic agents, wound-healing agents, or combinations thereof, useful in the treatment of external wounds. The active agents are encapsulated in liposomes, and the liposomes are incorporated in pharmaceutical preparations such as liquids, ointments, gels, lotions, or creams capable of delivering the active agents to external wound sites. The invention further relates to methods of preparation of the liposomes and the pharmaceutical preparations, and to methods of treatment of external wounds and ophthalmic infections. | 09-30-2010 |
20120177725 | PREPARATIONS FOR THE EXTERNAL APPLICATION OF ANTISEPTIC AGENTS AND/OR AGENTS PROMOTING THE HEALING OF WOUNDS - The present invention relates to liposomal pharmaceutical preparations which include active agents such as antiseptic agents, wound-healing agents, or combinations thereof, useful in the treatment of external wounds. The active agents are encapsulated in liposomes, and the liposomes are incorporated in pharmaceutical preparations such as liquids, ointments, gels, lotions, or creams capable of delivering the active agents to external wound sites. The invention further relates to methods of preparation of the liposomes and the pharmaceutical preparations, and to methods of treatment of external wounds and ophthalmic infections. | 07-12-2012 |
Patent application number | Description | Published |
20100173847 | TFPI INHIBITORS AND METHODS OF USE - The invention provides peptides that bind Tissue Factor Pathway Inhibitor (TFPI), including TFPI-inhibitory peptides, and compositions thereof. The peptides may be used to inhibit a TFPI, enhance thrombin formation in a clotting factor-deficient subject, increase blood clot formation in a subject, and/or treat a blood coagulation disorder in a subject. | 07-08-2010 |
20100234344 | 8-OXY-QUINOLINE DERIVATIVES AS BRADYKININ B2 RECEPTOR MODULATORS - The present invention is related to compound of the formula (I): or a pharmacologically acceptable salt, solvate, or hydrate thereof, wherein A is a 6-membered heteroaryl having from 1 to 3 heteroatoms, each independently selected from N or O and the other substituents are defined as in the claims. | 09-16-2010 |
20110077381 | NOVEL NPR-B AGONISTS - Disclosed are novel compounds having NPR-B agonistic activity. Preferred compounds are linear peptides containing 8-13 conventional or non-conventional L- or D-amino acid residues connected to one another via peptide bonds. | 03-31-2011 |
20130274193 | TFPI INHIBITORS AND METHODS OF USE - The invention provides peptides that bind Tissue Factor Pathway Inhibitor (TFPI), including TFPI-inhibitory peptides, and compositions thereof. The peptides may be used to inhibit a TFPI, enhance thrombin formation in a clotting factor-deficient subject, increase blood clot formation in a subject, and/or treat a blood coagulation disorder in a subject. | 10-17-2013 |
20130345394 | NOVEL NPR-B AGONISTS - Disclosed are novel compounds having NPR-B agonistic activity. Preferred compounds are linear peptides containing 8-13 conventional or non-conventional L- or D-amino acid residues connected to one another via peptide bonds. | 12-26-2013 |