Patent application number | Description | Published |
20080298261 | Reconfigurable Test System - There is disclosed a reconfigurable network test system. The reconfigurable test system may include a plurality of test modules, a plurality of network interface units, a plurality of bypass units, and a multi-port switch. Each of the network interface units may have a first end and a second end adapted to be connected to a network. Each bypass unit may be in communication with an associated test module, the first end of an associated network interface unit, a first associated switch port, and a second associated switch port. Each bypass unit may have a first mode wherein the associated test module is placed in communication with the first end of the associated network interface unit, and a second mode wherein the associated test module is placed in communication with the first associated switch port and the associated network interface unit is placed in communication with the second associated switch. | 12-04-2008 |
20080298380 | Transmit Scheduling - There are disclosed apparatus and methods for scheduling packet transmission. At least one scheduled traffic queue holds a plurality of scheduled packets, each scheduled packet having an associated scheduled transmit time. At least one unscheduled traffic queue holds plurality of unscheduled packets. A packet selector causes transmission of scheduled packets from the scheduled traffic queue at the associated scheduled transmit time, while causing transmission of unscheduled packets from the unscheduled traffic queue during the time intervals between transmissions of scheduled packets. | 12-04-2008 |
20110075681 | HIGH SPEED RING/BUS - A data communication bus and method of operation thereof, including a plurality of nodes connected to a respective plurality of media segments. A typical node includes an output port coupled to a media segment that it exclusively controls. And an input port coupled to a media segment that is exclusively controlled by another node of the bus. Each media segment typically includes a plurality of high speed data channels such as electrical transmission lines. | 03-31-2011 |
20120120819 | Testing Packet Fragmentation - Methods and apparatus for testing a network that converts datagrams into fragments. A traffic generator may generate a datagram containing plural instrumentation blocks and transmit the test traffic over the network. A traffic receiver may determine if a plurality of fragments received via the network constitutes a complete datagram based, at least in part, on data within respective instrumentation blocks extracted from each received fragment. The traffic receiver may report test statistics indicative of a number of complete datagrams received and a number of incomplete datagrams received. | 05-17-2012 |
20120120820 | Testing Fragment Reassembly - Methods and apparatus for testing a network that reassembles fragments into datagrams. A packet receiver may extract a plurality of instrumentation blocks from a packet received from the network. The packet receiver may determine if the received packet constitutes a correctly reassembled datagram based on information contained within the plurality of instrumentation blocks. The packet receiver may accumulate and report test statistics indicative of a number of correctly reassembled datagrams received and a number of incorrectly reassembled datagrams received. | 05-17-2012 |
20140043981 | GENERATING PACKETS TO TEST FRAGMENTATION - Methods, apparatus and machine readable storage media for testing fragmentation of datagrams by a network under test. A traffic generator may generate a datagram including a header and a payload, the payload containing plural instrumentation blocks, each instrumentation block containing information identifying the datagram and information identifying the location of each instrumentation block within the datagram. The traffic generator may transmit the datagram over the network under test. | 02-13-2014 |
20140298335 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR EMULATING VIRTUALIZATION RESOURCES - Methods, systems, and computer readable media for emulating virtualization resources are disclosed. According to one method, the method occurs at a computing platform. The method includes receiving a message associated with a device under test (DUT) and in response to receiving the message, performing an action associated with at least one of an emulated hypervisor and an emulated virtual machine (VM). | 10-02-2014 |
20140301405 | HIGH SPEED RING/BUS - A data communication bus and method of operation thereof, including a plurality of nodes connected to a respective plurality of media segments. A typical node includes an output port coupled to a media segment that it exclusively controls. And an input port coupled to a media segment that is exclusively controlled by another node of the bus. Each media segment typically includes a plurality of high speed data channels such as electrical transmission lines. | 10-09-2014 |
Patent application number | Description | Published |
20110075681 | HIGH SPEED RING/BUS - A data communication bus and method of operation thereof, including a plurality of nodes connected to a respective plurality of media segments. A typical node includes an output port coupled to a media segment that it exclusively controls. And an input port coupled to a media segment that is exclusively controlled by another node of the bus. Each media segment typically includes a plurality of high speed data channels such as electrical transmission lines. | 03-31-2011 |
20110314215 | MULTI-PRIORITY ENCODER - A multi-priority encoder includes a plurality of interconnected, single-priority encoders arranged in descending priority order. The multi-priority encoder includes circuitry for blocking a match output by a lower level single-priority encoder if a higher level single-priority encoder outputs a match output Match data is received from a content addressable memory, and the priority encoder includes address encoding circuitry for outputting the address locations of each highest priority match line flagged by the highest priority indicator. Each single-priority encoder includes a highest priority indicator which has a plurality of indicator segments, each indicator segment being associated with a match line input. | 12-22-2011 |
20130265813 | MULTI-PRIORITY ENCODER - A multi-priority encoder includes a plurality of interconnected, single-priority encoders arranged in descending priority order. The multi-priority encoder includes circuitry for blocking a match output by a lower level single-priority encoder if a higher level single-priority encoder outputs a match output. Match data is received from a content addressable memory, and the priority encoder includes address encoding circuitry for outputting the address locations of each highest priority match line flagged by the highest priority indicator. Each single-priority encoder includes a highest priority indicator which has a plurality of indicator segments, each indicator segment being associated with a match line input. | 10-10-2013 |
20140301405 | HIGH SPEED RING/BUS - A data communication bus and method of operation thereof, including a plurality of nodes connected to a respective plurality of media segments. A typical node includes an output port coupled to a media segment that it exclusively controls. And an input port coupled to a media segment that is exclusively controlled by another node of the bus. Each media segment typically includes a plurality of high speed data channels such as electrical transmission lines. | 10-09-2014 |