# Rarick, CA

## Inger Rarick, Portola Valley, CA US

Patent application number | Description | Published |
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20080294490 | Networking Platform For Facilitating Interactions And Sharing Of Caretaking Responsibilities Between Family Members - Systems and methods of a networking platform for facilitating interactions and sharing of caretaking responsibilities between family members are described in this application. In one aspect, embodiments of the present disclosure include a method, which may be implemented on a system, of managing a set of calendar events of the care receiver, the set of calendar events of the care receiver to be submitted by one or more of the care receiver a caregiver. One embodiment can include, generating a reminder associated with an upcoming occurrence of a calendar event of the set of calendar events at a predetermined amount of time prior to the upcoming occurrence, the reminder to be provided to one or more caregivers, updating a status of one or more of the set of calendar events based on an update provided by one or more of the care receiver the caregiver, identifying the schedules of the one or more care givers, and/or identifying at least one responsible caregiver to manage a calendar event of the care receiver by comparing the schedules of the one or more care givers with the set of calendar events. | 11-27-2008 |

20090307009 | WIDGET ASSOCIATED WITH NETWORKING PLATFORM - Systems and methods for enabling caregivers to communicate with care-receivers and share information and data are described. The care-receiver may use a family-oriented networking platform as it provides an easy and intuitive way to stay in touch with their families and healthcare professionals. The objective of the present invention is to allow caregivers to use their preferred means of digital communication to communicate with the care-receivers | 12-10-2009 |

## Inger Rarick, San Mateo County, CA US

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20080294462 | System, Method, And Apparatus Of Facilitating Web-Based Interactions Between An Elderly And Caregivers - Systems, methods and apparatuses of facilitating web-based interactions between an elderly and caregivers are described in this application. In one aspect, embodiments of the present disclosure include a method, which may be implemented on a system, of providing care through facilitating interactions between a set of service subscribers including an elderly and one or more caregivers, via an online networking platform. One embodiment can include, receiving data provided by one or more remote users, the data to be provided to a local user based on a time frame indicated by a request generated by the one or more remote users, providing the data to the local user via a network connection, the data to be displayed on a display screen to be provided to the local user, receiving data provided by the local user to be transmitted to the one or more remote users, and/or transmitting the data provided by the local user to the one or more remote users via the network connection, upon receiving a request generated by the local user, the one or more remote users being a caregiver and wherein the local user being the elderly | 11-27-2008 |

## Leonard Rarick, San Diego, CA US

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20160034256 | FAST INTEGER DIVISION - Embodiments disclosed pertain to apparatuses, systems, and methods for fast integer division. Disclosed embodiments pertain to an integer divide circuit to divide a dividend by a divisor and produce multiple quotient bits per iteration. In some embodiments, the fast integer divider may include a partial remainder register initialized with the dividend. Further, the fast integer divider circuit may include a plurality of adders, where each adder subtracts a multiple of the divisor from the current value in the partial remainder register. A logic block coupled to each of the adders, determines multiple quotient bits at each iteration based on the subtraction results. | 02-04-2016 |

## Leonard D. Rarick, San Jose, CA US

Patent application number | Description | Published |
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20090172054 | EFFICIENT LEADING ZERO ANTICIPATOR - Embodiments of the present invention provide a system that estimates the location of the leading zero or the leading one in the result of an addition of floating-point numbers A and B. The system includes a half-adder circuit associated with each separate bit position i in A and B. The half-adder circuits compute a sum (S) for the associated bit position of A and B and a carry (K) for a next bit position of A and B. The system also includes a set of estimation circuits coupled to the set of half-adder circuits. The set of estimation circuits computes an estimate for the location of the leading zero or the leading one in the result from the K and S computed by each half-adder circuit. | 07-02-2009 |

20090287757 | Leading Zero Estimation Modification for Unfused Rounding Catastrophic Cancellation - Modifying a leading zero estimation during an unfused multiply add operation of (A*B)+C. A plurality of terms x and y may be received, and each may be based on truncated terms s and t (e.g., in performing the unfused multiply add operation) and the shifted C term. A first leading zero estimation may be calculated based on the terms x and y. It may be determined if near total catastrophic cancellation has occurred. A carry in from a right most number of bits of the terms s and t and the most significant truncated bits of s and t may be used to generate a second leading zero estimation based on the first leading zero estimation if the near total catastrophic cancellation has occurred. | 11-19-2009 |

20100036901 | MODULUS-BASED ERROR-CHECKING TECHNIQUE - During a method, a modulus circuit determines a modulus base p of a first number and a modulus base p of a second number. Also, the modulus circuit performs the operation using the modulus base p of the first number and the modulus base p of the second number, and calculates a modulus base p of the result of the operation involving the first number and the second number. Next, the modulus circuit compares the result of the operation carried out on the modulus base p of the first number and the modulus base p of the second number with the modulus base p of the operation performed on the first number and the second number to identify potential errors associated with the operation. Moreover, the modulus circuit repeats the method to identify additional potential errors associated with the operation, where the determining and calculating operations are repeated using moduli base q. | 02-11-2010 |

20100057824 | METHOD AND SYSTEM FOR PROCESSING THE BOOTH ENCODING 33RD TERM - A computer system for computing a binary operation involving a first term multiplied by a second term resulting in a product, where the product is conditionally added to a third term in a central processing unit. The central processing unit includes a carry save adder configured to add a plurality of partial products obtained from the product of the first term and the second term to obtain a first partial result and a second partial result, a multiplexer configured to output one selected from the group consisting of the second term, the third term, and zero, and an alignment shifter configured to shift an output of the multiplexer to align the output of the multiplexer with the first partial result and the second partial result to obtain a shifted term. The shifted term, the first partial result and the second partial result are added together to obtain a result of the binary operation. | 03-04-2010 |

20100329450 | INSTRUCTIONS FOR PERFORMING DATA ENCRYPTION STANDARD (DES) COMPUTATIONS USING GENERAL-PURPOSE REGISTERS - Some embodiments of the present invention provide a processor, which includes a set of general-purpose registers and at least one execution unit. Each general-purpose register in the set of general-purpose registers is at least 64 bits wide, and the execution unit supports one or more Data Encryption Standard (DES) instructions. Specifically, the execution unit may support a permutation-rotation instruction for performing DES permutation operations and DES rotation operations. The execution unit may also support a round instruction to perform a DES round operation. Since the DES instructions use general-purpose registers instead of special-purpose registers to perform DES-specific operations, the processor's circuit complexity and area are reduced. Furthermore, in some embodiments, since the DES instructions require at most two operands, the number of bits required to specify the location of the operands are reduced, thereby enabling a larger number of instructions to be supported by the processor. | 12-30-2010 |

20120041997 | FUSED MULTIPLY-ADD ROUNDING AND UNFUSED MULTIPLY-ADD ROUNDING IN A SINGLE MULTIPLY-ADD MODULE - A computer processor including a single fused-unfused floating point multiply-add (FMA) module computes the result of the operation A*B+C for floating point numbers for fused multiply-add rounding operations and unfused multiply-add rounding operations. In one embodiment, a fused multiply-add rounding implementation is augmented with additional hardware which calculates an unfused multiply-add rounding result without adding additional pipeline stages. In one embodiment, a computation by the fused-unfused floating point multiply-add (FMA) module is initiated using a single opcode which determines whether a fused multiply-add rounding result or unfused multiply-add rounding result is generated. | 02-16-2012 |

## Leonard D. Rarick, San Diego, CA US

Patent application number | Description | Published |
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20080317244 | EXECUTION UNIT FOR PERFORMING THE DATA ENCRYPTION STANDARD - An execution unit adapted to perform at least a portion of the Data Encryption Standard. The execution unit includes a Left Half input; a Key input; and a Table input. The execution unit also includes a first group of transistors configured to receive the Table input, perform a table look-up, and output data. The execution unit further includes a first exclusive-or operator having two inputs and an output. The first exclusive-or operator is configured to receive the Left Half input and the Key input. The execution unit also includes a second exclusive-or operator having two inputs and an output. The second exclusive-or operator is configured to receive the data output by the first group of transistors and to receive the output of the first exclusive-or operator. The execution unit also includes a third exclusive-or operator having two inputs and an output. The third exclusive-or operator is configured to receive the Left Half input and the data output by the first group of transistors. | 12-25-2008 |

20120087492 | EXECUTION UNIT FOR PERFORMING THE DATA ENCRYPTION STANDARD - Described is an execution unit for performing at least part of the Data Encryption Standard that includes a Left Half input; a Key input; and a Table input, as well as a first group of transistors configured to receive the Table input, perform a table look-up, and output data. The execution unit further includes a first exclusive-or operator having two inputs and an output that is configured to receive the Left Half input and the Key input. The execution unit also includes a second exclusive-or operator having two inputs and an output that is configured to receive the data output by the first group of transistors and to receive the output of the first exclusive-or operator. The execution unit also includes a third exclusive-or operator having two inputs and an output that is configured to receive the Left Half input and the data output by the first group of transistors. | 04-12-2012 |

20140006470 | Carry Look-Ahead Adder with Generate Bits and Propagate Bits Used for Column Sums | 01-02-2014 |