Patent application number | Description | Published |
20120246529 | LOW-POWER AND AREA-EFFICIENT SCAN CELL FOR INTEGRATED CIRCUIT TESTING - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells, with the scan chain being configured to operate as a serial shift register in a scan shift mode of operation and to capture functional data from at least a portion of the additional circuitry in a functional mode of operation. At least a given one of the scan cells of the scan chain comprises output control circuitry which is configured to disable a functional data output of the scan cell in the scan shift mode of operation and to disable a scan output of the scan cell in the functional mode of operation. | 09-27-2012 |
20120324303 | INTEGRATED CIRCUIT COMPRISING SCAN TEST CIRCUITRY WITH PARALLEL REORDERED SCAN CHAINS - An integrated circuit comprises scan test circuitry and additional internal circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains, with each such scan chain comprising a plurality of flip-flops configurable to operate as a serial shift register. The plurality of scan chains are arranged in sets of two or more parallel scan chains. The scan test circuitry further comprises multiplexing circuitry, including a plurality of multiplexers each associated with a corresponding one of the sets of parallel scan chains and configured to multiplex scan test outputs from the parallel scan chains within the corresponding one of the sets of parallel scan chains. In one embodiment, one or more of the sets of parallel scan chains comprise respective pairs of parallel scan chains with each such pair corresponding to a single original scan chain. A given one of the pairs of parallel scan chains comprises an even scan chain and an odd scan chain, formed by reordering the corresponding single original scan chain. | 12-20-2012 |
20120331362 | INTEGRATED CIRCUIT COMPRISING SCAN TEST CIRCUITRY WITH CONTROLLABLE NUMBER OF CAPTURE PULSES - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains coupled to the additional circuitry, a scan capture clock generator configured to generate a scan capture clock signal having a controllable number of capture pulses, and a clock selection circuit configured to select between at least the scan capture clock signal and a scan shift clock signal for application to clock signal inputs of the scan chains. In one embodiment, the scan capture clock generator comprises a finite state machine, a plurality of capture clock pulse circuits each generating a capture clock pulse signal comprising a different number of capture clock pulses, and logic circuitry coupled to the finite state machine and having inputs adapted to receive the outputs of the capture clock pulse circuits. The logic circuitry is configured to provide at an output thereof at least a portion of a particular one of the capture clock pulse signals based on a current state of the finite state machine. | 12-27-2012 |
20130007547 | EFFICIENT WRAPPER CELL DESIGN FOR SCAN TESTING OF INTEGRATED CIRCUITS - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains, including at least one wrapper cell scan chain arranged between first and second circuitry cores of the additional circuitry, with the wrapper cell scan chain comprising a plurality of wrapper cells and being configurable to operate as a serial shift register in a scan shift mode of operation. At least one of the wrapper cells of the wrapper cell scan chain comprises a flip-flop having a throughput data path that is part of a scan shift path of the wrapper cell scan chain and not part of a functional path between the first and second circuitry cores. In an HDD controller embodiment, the first and second circuitry cores may comprise respective read channel and additional cores of a system-on-chip. | 01-03-2013 |
20130055041 | Scan Test Circuitry Comprising Scan Cells with Multiple Scan Inputs - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises scan cells configured to form scan chains. At least a given one of the scan cells is a multiple scan input scan cell having at least first and second scan inputs. In a first scan shift mode of operation, the given scan cell is configured with a first plurality of other scan cells into a scan chain of a first type using the first scan input. In a second scan shift mode of operation, the given scan cell is configured with a second plurality of other scan cells different than the first plurality of other scan cells into a scan chain of a second type using the second scan input. | 02-28-2013 |
20130067290 | INTEGRATED CIRCUIT WITH TRANSITION CONTROL CIRCUITRY FOR LIMITING SCAN TEST SIGNAL TRANSITIONS DURING SCAN TESTING - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises transition control circuitry configured to detect transitions between binary logic levels in a scan test signal, and responsive to a number of detected transitions reaching a threshold, to limit further transitions associated with a remaining portion of the scan test signal. In an illustrative embodiment, the transition control circuitry limits further transitions associated with the remaining portion of the scan test signal by replacing at least part of the remaining portion of the scan test signal with a limited transition signal. The limited transition signal may be maintained at a constant binary logic level such that it has no transitions. By limiting the number of transitions associated with the scan test signal, the transition control circuitry serves to reduce integrated circuit power consumption during scan testing. | 03-14-2013 |
20130103994 | DYNAMIC CLOCK DOMAIN BYPASS FOR SCAN CHAINS - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of sub-chains associated with respective distinct clock domains, and clock domain bypass circuitry configured to selectively bypass one or more of the sub-chains. The scan chain is configurable in a scan shift mode of operation to form a serial shift register that includes fewer than all of the sub-chains with at least a remaining one of the sub-chains being bypassed by the clock domain bypass circuitry so as to not be part of the serial shift register in the scan shift mode. By selectively bypassing portions of the scan chain associated with particular clock domains, the clock domain bypass circuitry serves to reduce test time and power consumption during scan testing. | 04-25-2013 |
20130111286 | SCAN ENABLE TIMING CONTROL FOR TESTING OF SCAN CELLS | 05-02-2013 |
20130124594 | DIVIDER CIRCUITRY WITH QUOTIENT PREDICTION BASED ON ESTIMATED PARTIAL REMAINDER - An integrated circuit comprises divider circuitry configured to perform a division operation. The divider circuitry may be part of an arithmetic logic unit or other computational unit of a microprocessor, digital signal processor, or other type of processor. The divider circuitry iteratively determines bits of a quotient over multiple stages of computation. In determining the quotient in one embodiment, the divider circuitry is configured to estimate a partial remainder for a given one of the stages and to predict one or more of the quotient bits for one or more subsequent stages based on the estimated partial remainder so as to allow one or more computations to be skipped for said one or more subsequent stages, thereby reducing power consumption. The integrated circuit may be incorporated in a computer, a mobile telephone, a storage device or other type of processing device. | 05-16-2013 |
20130173976 | Scan Test Circuitry with Delay Defect Bypass Functionality - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells. The scan test circuitry further comprises scan delay defect bypass circuitry comprising a plurality of multiplexers arranged within said at least one scan chain. At least a given one of the multiplexers is configured to allow a corresponding one of the scan cells to be selectively bypassed in a scan shift configuration of the scan cells responsive to a delay defect associated with that scan cell. A delay defect bypass controller may be used to generate a bypass control signal for controlling the multiplexer between at least a first state in which the corresponding scan cell is not bypassed and a second state in which the corresponding scan cell is bypassed. | 07-04-2013 |
20130179742 | SCAN CHAIN LOCKUP LATCH WITH DATA INPUT CONTROL RESPONSIVE TO SCAN ENABLE SIGNAL - A scan chain lockup latch comprises at least one latching element and data input control circuitry configured to control application of data to a data input of the latching element responsive to a scan enable signal. The lockup latch is configured for coupling between first and second scan cells of a scan chain. The scan chain may be controllable between a scan shift mode of operation and a functional mode of operation responsive to the scan enable signal. The data input control circuitry may be configured to maintain the data input of the latching element at a constant logic value when the scan chain is in its functional mode of operation such that switching activity in the latching element is suppressed. The scan chain lockup latch and the associated scan chain may be implemented in scan test circuitry of an integrated circuit, for testing additional circuitry of that integrated circuit. | 07-11-2013 |
20130181852 | CODING CIRCUITRY FOR DIFFERENCE-BASED DATA TRANSFORMATION - Coding circuitry for difference-based data transformation in an illustrative embodiment comprises a difference-based encoder having a plurality of processing stages, with the difference-based encoder being configured to generate respective orders of difference from a sequence of data samples and to output encoded data determined based on at least a selected one of the orders of difference. The coding circuitry may be configured to implement lossless, linear compression of the sequence of data samples. The coding circuitry may additionally or alternatively comprise a difference-based decoder having a plurality of processing stages, with the difference-based encoder being configured to process encoded data comprising selected ones of a plurality of orders of difference and to reconstruct a sequence of data samples based on the selected orders of difference. | 07-18-2013 |
20130185607 | SCAN TEST CIRCUITRY CONFIGURED FOR BYPASSING SELECTED SEGMENTS OF A MULTI-SEGMENT SCAN CHAIN - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells, wherein the scan chain is separated into a plurality of scan segments with each such segment comprising a distinct subset of two or more of the plurality of scan cells. The scan test circuitry further comprises scan segment bypass circuitry configured to selectively bypass one or more of the scan segments in a scan shift mode of operation. The scan segment bypass circuitry may comprise a plurality of multiplexers and a scan segment bypass controller. The multiplexers are arranged within the scan chain and configured to allow respective ones of the scan segments to be bypassed responsive to respective bypass control signals generated by the scan segment bypass controller. | 07-18-2013 |
20130219238 | INTEGRATED CIRCUIT HAVING CLOCK GATING CIRCUITRY RESPONSIVE TO SCAN SHIFT CONTROL SIGNAL - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells. The integrated circuit further comprises a clock distribution network configured to provide clock signals to respective portions of the integrated circuit. The clock distribution network comprises clock gating circuitry configured to control delivery of one or more of the clock signals along respective clock signal lines of the clock distribution network at least in part responsive to a scan shift control signal that is also utilized to cause the scan cells to form a serial shift register during scan testing. The clock gating circuitry may be used to determine whether a clock delay defect that causes a scan error during scan testing will also cause a functional error during functional operation, thereby improving yield in integrated circuit manufacturing. | 08-22-2013 |
20130290799 | SCAN TEST CIRCUITRY WITH SELECTABLE TRANSITION LAUNCH MODE - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having scan cells. The scan test circuitry further comprises transition launch mode selection circuitry configured to provide independent selection between multiple transition launch modes for each of a plurality of clock domains of the integrated circuit. The multiple transition launch modes may include, for example, at least a launch-on-shift mode and a launch-on-capture mode. These transition launch modes provide different manners of launching a given signal transition via at least one of the scan cells in a corresponding one of the clock domains. The transition launch mode selection circuitry may be configured to generate from a common shift enable signal multiple independently controllable shift enable signals for respective ones of the clock domains of the integrated circuit. | 10-31-2013 |
20130311843 | SCAN CONTROLLER CONFIGURED TO CONTROL SIGNAL VALUES APPLIED TO SIGNAL LINES OF CIRCUIT CORE INPUT INTERFACE - An integrated circuit comprises a memory or other circuit core having an input interface and an output interface, scan circuitry comprising at least one scan chain having a plurality of scan cells, and additional circuitry associated with at least one of the input interface and the output interface and testable utilizing said at least one scan chain. The scan circuitry further comprises a scan controller configured to control signal values applied to one or more signal lines of the input interface in conjunction with testing of the additional circuitry utilizing said at least one scan chain. For example, the scan controller may control signal values applied to respective address input and write enable signal lines in a manner that ensures that data written to a memory in a write operation of a given memory cycle can be read from the memory in a read operation of a subsequent memory cycle. | 11-21-2013 |
20140032985 | SCAN TEST CIRCUITRY CONFIGURED TO PREVENT CAPTURE OF POTENTIALLY NON-DETERMINISTIC VALUES - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having scan cells. The scan test circuitry is configured to control at least a given one of the scan cells so as to prevent the scan cell from capturing a potentially non-deterministic value from a portion of the additional circuitry. The portion of the additional circuitry that provides the potentially non-deterministic value may comprise, for example, at least one of a mixed signal logic block and a memory block of the additional circuitry. The given scan cell may be controlled by configuring the scan cell such that it is unable to capture data in a scan capture mode of operation in which it would otherwise normally be able to capture data. | 01-30-2014 |
20140068229 | INSTRUCTION ADDRESS ENCODING AND DECODING BASED ON PROGRAM CONSTRUCT GROUPS - Coding circuitry comprises at least an encoder configured to encode an instruction address for transmission to a decoder. The encoder is operative to identify the instruction address as belonging to a particular one of a plurality of groups of instruction addresses associated with respective distinct program constructs, and to encode the instruction address based on the identified group. The decoder is operative to identify the encoded instruction address as belonging to the particular one of a plurality of groups of instruction addresses associated with respective distinct program constructs, and to decode the encoded instruction address based on the identified group. The coding circuitry may be implemented as part of an integrated circuit or other processing device that includes associated processor and memory elements. In such an arrangement, the processor may generate the instruction address for delivery over a bus to the memory. | 03-06-2014 |
20140101501 | SCAN TEST CIRCUITRY CONFIGURED TO PREVENT VIOLATION OF MULTIPLEXER SELECT SIGNAL CONSTRAINTS DURING SCAN TESTING - An integrated circuit comprises a decoder having a plurality of select signal outputs, a multiplexer having a plurality of select signal inputs subject to a specified select signal constraint, and scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells coupled between respective ones of the select signal outputs of the decoder and respective ones of the select signal inputs of the multiplexer. The scan test circuitry is configured to control at least a given one of the scan cells so as to prevent violation of the select signal constraint in conjunction with scan testing. The multiplexer may be, for example, a one-hot multiplexer for which the select signal constraint indicates that only one of the select signal inputs should receive a logic high select signal at a particular time. | 04-10-2014 |
20140143621 | SCAN CIRCUITRY FOR TESTING INPUT AND OUTPUT FUNCTIONAL PATHS OF AN INTEGRATED CIRCUIT - An integrated circuit comprises scan test circuitry, additional circuitry subject to testing utilizing the scan test circuitry, and control circuitry associated with the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells, and the associated control circuitry is coupled to at least a given one of a primary input of the integrated circuit and a primary output of the integrated circuit. The scan test circuitry is configurable by the control circuitry so as to permit testing of both an input functional path associated with the given one of the primary input and the primary output and an output functional path associated with the given one of the primary input and the primary output. | 05-22-2014 |
20140149812 | SCAN TEST CIRCUITRY WITH CONTROL CIRCUITRY CONFIGURED TO SUPPORT A DEBUG MODE OF OPERATION - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains each having a plurality of scan cells. The scan test circuitry further comprises control circuitry comprising first switching elements configured to control selective application of respective scan input signals to respective scan inputs of respective ones of the plurality of scan chains and second switching elements configured to control selective application of a shift enable signal to respective shift enable inputs of the respective ones of the plurality of scan chains. By appropriate control of the switching elements using test data register bits or other scan chain specific control signals, one or more debug modes can be supported by the scan test circuitry of the integrated circuit. | 05-29-2014 |
20140201584 | SCAN TEST CIRCUITRY COMPRISING AT LEAST ONE SCAN CHAIN AND ASSOCIATED RESET MULTIPLEXING CIRCUITRY - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells. The scan test circuitry further comprises control circuitry configured to control selective application of at least a particular one of a plurality of reset signals to reset inputs of at least a subset of the scan cells of the scan chain. For example, the control circuitry may comprise a first reset multiplexer configured to select between a first functional mode reset signal and a first scan mode reset signal for application to reset inputs of respective scan cells of the scan chain, and an additional multiplexer configured to select between an additional functional mode reset signal and an additional scan mode reset signal for application to reset inputs of respective internal flip-flops of the additional circuitry. | 07-17-2014 |
20140208175 | AT-SPEED SCAN TESTING OF CLOCK DIVIDER LOGIC IN A CLOCK MODULE OF AN INTEGRATED CIRCUIT - An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells. The integrated circuit further comprises a clock distribution network configured to provide clock signals to respective portions of the integrated circuit. The clock distribution network comprises at least one clock module comprising one or more clock dividers and associated clock divider logic, and the scan test circuitry is configured to permit testing of at least a portion of the clock divider logic. A given scan chain of the scan test circuitry may comprise first and second scan cells, with the first scan cell having a scan output coupled to a scan input of the second scan cell, and the second scan cell having a data input driven by an output of the clock divider logic. | 07-24-2014 |
20140281703 | Local Repair Signature Handling for Repairable Memories - A method is disclosed for independent repair signature load into a repairable memory within a chip set of a design without halting operation of other repairable memories within the design. At initial power up, the repair signature is received from nonvolatile memory and parallelly stored within a memory repair register and within a local memory repair shadow register. During intermediate power ups after an operational power savings scheme shut down, the method avoids serially re-loading the signature from the nonvolatile memory and loads the repair signature from the local memory repair shadow register. During local repair signature loading, the method disables the chip select for the memory to prevent memory operations until the repair signature is fully loaded. | 09-18-2014 |
20140289550 | Integrated Clock Architecture for Improved Testing - A computer system includes a first on-chip controller and a second on-chip controller, both connected to a control element. In normal operation, the first and second on-chip controllers operate in different clock domains. During testing, the control element causes each on-chip controller to generate a substantially similar clock signal. The substantially similar clock signals are used to test substantially similar test circuitry connected to each on-chip controller, thereby reducing overhead associated with testing. A delay may be incorporated into the path of the clock signal of one of the on-chip controllers to reduce instantaneous power draw during testing. | 09-25-2014 |
20140298123 | Scan Chain Reconfiguration and Repair - A system includes an integrated circuit. The integrated circuit includes at least one scan chain group. A particular scan chain group of the at least one scan chain group includes at least one scan chain and at least one spare scan chain. The at least one scan chain of the particular scan chain group includes a particular scan chain. The at least one spare scan chain of the particular scan chain group includes a particular spare scan chain. The particular spare scan chain is configured to bypass the particular scan chain. | 10-02-2014 |
20140304562 | Method for Testing Paths to Pull-Up and Pull-Down of Input/Output Pads - A SCAN chain architecture for each path in a circuit having combinational paths includes a control mechanism to control one or more flip flops and multiplexers to direct operational or test signals. Operational signals are sent along at least one combinational path to a pull-up/pull-down for at least one input/output pad and an operational voltage is recorded. Test signals are sent along at least one alternative path to an alternative input/output and a test voltage is recorded. The operational voltage is compared to the test voltage to identify a combinational path fault. | 10-09-2014 |
20140365838 | INTEGRATED CIRCUIT COMPRISING TEST CIRCUITRY FOR TESTING FAN-OUT PATHS OF A TEST CONTROL PRIMARY INPUT - An integrated circuit comprises a primary input adapted to receive a test control signal, a primary output, and logic circuits having inputs coupled to the primary input via respective fan-out paths of the primary input. The integrated circuit further includes first test circuitry configured for testing a designated portion of the integrated circuit in a first test mode of operation with the test control signal at a first logic value, and second test circuitry coupled between the inputs of the logic circuits and the primary output and configured for testing of the fan-out paths in a second test mode of operation in which the test control signal takes on both the first logic value and a second logic value associated with a functional mode of operation. The primary input, primary output, logic circuits and test circuitry may be associated with a particular circuit core of the integrated circuit. | 12-11-2014 |