Patent application number | Description | Published |
20080243461 | METHOD AND APPARATUS FOR THERMAL MODELING AND ANALYSIS OF SEMICONDUCTOR CHIP DESIGNS - A method and apparatus for modeling and thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal testing of a semiconductor chip design includes calculating full-chip temperatures over the semiconductor chip design (e.g., to identify steep thermal gradients) and modeling the full-chip temperatures in accordance with a geometric multi-grid technique. The geometric multi-grid technique is tailored to determine temperatures within the semiconductor chip design based at least in part on the physical attributes or geometry of the design. | 10-02-2008 |
20090019411 | Thermally Aware Design Modification - In a first variation, a thermally aware design automation suite integrates system-level thermal awareness into design of semiconductor chips, performing fine-grain thermal simulations of the chips based on thermal models and boundary conditions. The suite uses results of the simulations to modify thermally significant structures to achieve desired thermal variations across a chip, meet design assertions on selected portions of the chip, and verify overall performance and reliability of the chip over designated operating ranges and manufacturing variations. In a second variation, a discretization approach models chip temperature distributions using heuristics to adaptively grid space in three dimensions. Adaptive and locally variable grid spacing techniques are used to efficiently and accurately converge for steady state and/or transient temperature solutions. The modeling optionally reads a mesh initialization file specifying selected aspects and parameters associated with controlling use and behavior of the variable grid spacing techniques. | 01-15-2009 |
20090024347 | Thermal Simulation Using Adaptive 3D and Hierarchical Grid Mechanisms - A thermally aware design automation suite integrates system-level thermal awareness into design of semiconductor chips, performing fine-grain static and/or transient thermal simulations of the chips based on thermal models and boundary conditions. The thermal simulations are performed in accordance with one or more grids, with boundaries and/or resolutions being determined by adaptive and/or hierarchical multi-dimensional techniques. The adaptive grid techniques include material-boundary, rate-of-change, and convergence-information heuristics. For example, a finer grid is used in a region having higher temperature gradients compared to a region having lower temperature gradients. The hierarchical grid techniques are based on critical, intermediate, and boundary regions specified manually or automatically, each region having a respective grid resolution. For example, a critical region is analyzed according to a grid that is finer than a grid of an intermediate region, and resolution of a grid of a boundary region is adapted to boundary conditions. | 01-22-2009 |
20090024969 | SEMICONDUCTOR CHIP DESIGN HAVING THERMAL AWARENESS ACROSS MULTIPLE SUB-SYSTEM DOMAINS - A thermally aware design automation suite integrates system-level thermal awareness into the design of semiconductor chips. A thermal analysis engine performs fine-grain thermal simulations of the semiconductor chip based on thermal models and boundary conditions for all thermally significant structures in the chip and the adjacent system that impact the temperature of the semiconductor chip. The thermally aware design automation suite uses the simulations of the thermal analysis engine to repair or otherwise modify the thermally significant structures to equalize temperature variations across the chip, impose specified design assertions on selected portions of the chip, and verify overall chip performance and reliability over designated operating ranges and manufacturing variations. The thermally significant structures are introduced or modified via one or more of: change in number, change in location, and change in material properties. | 01-22-2009 |
20090044156 | METHOD AND APPARATUS FOR NORMALIZING THERMAL GRADIENTS OVER SEMICONDUCTOR CHIP DESIGNS - A method and apparatus for normalizing thermal gradients over semiconductor chip designs is provided. One embodiment of a novel method for normalizing an expected thermal gradient includes determining a location of the thermal gradient in the semiconductor chip design and inserting at least one supplemental heat source into the semiconductor chip design such that the thermal gradient is normalized by heat dissipated by the supplemental heat source. | 02-12-2009 |
20090048801 | Method and apparatus for generating thermal test vectors - Temperature aware testing enables computation of thermal test vectors that are applied, via a tester, to a Device Under Test (DUT) to place various internal elements of the DUT at respective temperature operating points. The respective temperature operating points are selected to sensitize the DUT to measurements of selected temperature-dependent critical parameters, including frequency, leakage current behaviors, voltage drops, power profiles, thermal gradients, and absolute temperature. In operation, the thermal test vectors are applied to the DUT for a sufficient time for the DUT to reach thermal equilibrium, or alternatively for the internal elements to reach the respective temperature operating points. Subsequently critical parameter vectors are applied to enable measurement of one or more of the critical parameters. The critical parameter vectors are typically developed based in part on a multi-dimensional temperature map analysis of the DUT, using manufacturing process parameters and device physical design (or layout) information. | 02-19-2009 |
20090077508 | ACCELERATED LIFE TESTING OF SEMICONDUCTOR CHIPS - Improved techniques for accelerated life testing of a sample of semiconductor chips advantageously enable more effective testing and better estimation of lifetime. Full-chip temperature maps are computed at sets of operating and testing conditions. Evaluating the temperature maps enables operations such as: temperature-aware design changes, including adding and/or configuring heating elements, cooling elements, thermal diodes, or sensors; determination of accelerated testing conditions; avoidance of harmful conditions during accelerated testing; and the better estimation of lifetime. Iteration of the computing and the evaluating refines the accelerated testing conditions. Measuring actual testing conditions and computing a full-chip temperature map using the actual testing conditions enables the estimation of lifetime to account for the actual testing conditions. A lifetime acceleration factor map based, at least in part, on the temperature maps is used to produce the estimated lifetime. Failure analysis improves accuracy of the estimated lifetime. | 03-19-2009 |