Patent application number | Description | Published |
20080273375 | INTEGRATED CIRCUIT HAVING A MAGNETIC DEVICE - An integrated circuit having a magnetic device is disclosed. In one embodiment, the integrated circuit includes a reference structure having a first blocking temperature. A storage structure is provided made of a ferromagnetic material. An antiferromagnetic structure is provided having a second blocking temperature lower than the first blocking temperature. | 11-06-2008 |
20090016096 | Integrated Circuits; Method for Manufacturing an Integrated Circuit; Method for Decreasing the Influence of Magnetic Fields; Memory Module - Embodiments of the invention relate generally to integrated circuits, to a method for manufacturing an integrated circuit, to a method for decreasing the influence of magnetic fields, and to a memory module. In an embodiment of the invention, an integrated circuit having a magnetic tunnel junction is provided. The magnetic tunnel junction may include a free layer with a magnetization orientation that is selected by the application of a write current through the magnetic tunnel junction, and a retention layer that retains the selectable magnetization orientation of the free layer at temperatures below a retention temperature. | 01-15-2009 |
20090073737 | Integrated Circuits; Methods for Manufacturing an Integrating Circuit; Memory Modules - Embodiments of the invention relate generally to integrated circuits, to methods for manufacturing an integrating circuit, and to memory modules. In an embodiment of the invention, an integrated circuit is provided having a memory cell. The memory cell may include a first magnetic layer structure, a tunnel barrier layer structure disposed above the first magnetic layer structure, a second magnetic layer structure disposed above the tunnel barrier layer structure, and at least one sacrificial material layer to suppress electrochemical corrosion of the first magnetic layer structure or the second magnetic layer structure. | 03-19-2009 |
20090073750 | Method for Programming an Integrated Circuit, Methods for Programming a Plurality of Cells, Integrated Circuit, Cell Arrangement - Embodiment of the invention provide a method for programming an integrated circuit, methods for programming a plurality of cells, an integrated circuit, and a cell arrangement. An embodiment of the invention provides a method for programming an integrated circuit having a plurality of cells. The method includes grouping the plurality of cells into a first group of cells and a second group of cells depending on the cell state the cells should be programmed with. The first group of cells and the second group of cells each having a plurality of cells. The method further includes concurrently programming the cells of the first group of cells with a first cell state. After having programmed the cells of the first group of cells, the cells of the second group of cells are concurrently programmed with a second cell state, which is different from the first cell state. | 03-19-2009 |
20090230379 | Integrated Circuit, Method of Manufacturing an Integrated Circuit, and Memory Module - According to one embodiment of the present invention, an integrated circuit including a plurality of memory cells is provided. Each memory cell includes a resistivity changing memory element which includes a top electrode, a bottom electrode, and resistivity changing material being disposed between the top electrode and the bottom electrode. Each resistivity changing memory element is at least partially surrounded by a thermal insulating structure. The thermal insulating structures are arranged such that the dissipation of heat generated within the resistivity changing memory elements into the environment of the resistivity changing memory elements is lowered. | 09-17-2009 |
20090273044 | Semiconductor Device, Memory Module, and Method of Manufacturing a Semiconductor Device - According to one embodiment of the present invention, a semiconductor device is provided including a semiconductor chip. The semiconductor chip is at least partly surrounded by a surrounding structure. The semiconductor chip further includes a magneto-resistive memory cell. A shielding layer is disposed between the semiconductor chip and the surrounding structure, wherein the shielding layer is configured to shield the magneto-resistive memory cell from external magnetic fields. | 11-05-2009 |
20090273966 | Integrated Circuit, Memory Cell Array, Memory Module, and Method of Operating an Integrated Circuit - According to one embodiment of the present invention, an integrated circuit includes a plurality of thermal selectable memory cells, each memory cell being connected to a conductive line, the conductive line having a first portion for applying a heating current, and a second portion for applying a programming current. The integrated circuit is configured such that the heating current and the programming current can be routed respectively to the first and the second portion of the conductive line independently from each other. | 11-05-2009 |
20100002501 | MRAM Device Structure Employing Thermally-Assisted Write Operations and Thermally-Unassisted Self-Referencing Operations - A thermally-assisted MRAM structure which is programmable at a writing mode operating temperature is presented and includes an anti-ferromagnet, an artificial anti-ferromagnet, a barrier layer, and a free magnetic layer. The anti-ferromagnet is composed of a material having a blocking temperature T | 01-07-2010 |
20100032642 | Method of Manufacturing a Resistivity Changing Memory Cell, Resistivity Changing Memory Cell, Integrated Circuit, and Memory Module - According to an embodiment, a method of manufacturing an integrated circuit including a plurality of resistivity changing memory cells is provided. The method includes: forming a stack of layers including a resistivity changing layer, a first conductive layer, a second conductive layer, and a patterned masking layer which are stacked above each other in this order; patterning the second conductive layer using the masking layer as a patterning mask; patterning the first conductive layer using the second conductive layer as a patterning mask; and patterning the resistivity changing layer using the first conductive layer as a patterning mask. | 02-11-2010 |
20110073987 | Through Substrate Features in Semiconductor Substrates - Through substrate features in semiconductor substrates are described. In one embodiment, the semiconductor device includes a through substrate via disposed in a first region of a semiconductor substrate. A through substrate conductor coil is disposed in a second region of the semiconductor substrate. | 03-31-2011 |
20110073997 | Semiconductor Structure and Method for Making Same - One or more embodiments relate to a method for making a semiconductor structure, the method including: forming a first conductive interconnect at least partially through the substrate; and forming a second conductive interconnect over the substrate, wherein the first conductive interconnect and the second conductive interconnect are formed at least partially simultaneously. | 03-31-2011 |
20110241218 | Electronic Device and Manufacturing Method - A semiconductor package includes a semiconductor chip, an encapsulant embedding the semiconductor chip, first contact pads on a first main face of the semiconductor package and second contact pads on a second main face of the semiconductor package opposite to the first main face. The diameter d in micrometers of an exposed contact pad area of the second contact pads satisfies d≧(8/25)x+142 μm, wherein x is the pitch of the second contact pads in micrometers. | 10-06-2011 |
20120012949 | PRESSURE SENSOR PACKAGE SYSTEMS AND METHODS - Embodiments relate to integrated circuit (IC) sensors and sensing systems and methods. In an embodiment, an IC sensor device includes at least one sensing element; a framing element disposed around the at least one sensing element at a wafer-level; and a package having at least one port predefined at the wafer-level by the framing element, the at least one port configured to expose at least a portion of the at least one sensing element to an ambient environment. | 01-19-2012 |
20120208319 | Packaged Semiconductor Device with Encapsulant Embedding Semiconductor Chip that Includes Contact Pads - A method of manufacturing a semiconductor package includes embedding a semiconductor chip in an encapsulant. First contact pads are formed on a first main face of the semiconductor package and second contact pads are formed on a second main face of the semiconductor package opposite the first main face. A diameter d in micrometers of an exposed contact pad area of the second contact pads satisfies d≧(8/25)x+142 μm, where x is a pitch of the second contact pads in micrometers. | 08-16-2012 |
20140042565 | Apparatus Comprising and a Method for Manufacturing an Embedded MEMS Device - A system and a method for forming a packaged MEMS device are disclosed. In one embodiment a packaged MEMS device includes a MEMS device having a first main surface with a first area along a first direction and a second direction, a membrane disposed on the first main surface of the MEMS device and a backplate adjacent to the membrane. The packaged MEMS device further includes an encapsulation material that encapsulates the MEMS device and that defines a back volume, the back volume having a second area along the first direction and the second direction, wherein the first area is smaller than the second area. | 02-13-2014 |
20140103463 | MEMS SENSOR PACKAGE SYSTEMS AND METHODS - Embodiments relate to sensor and sensing devices, systems and methods. In an embodiment, a micro-electromechanical system (MEMS) device comprises at least one sensor element; a framing element disposed around the at least one sensor element; at least one port defined by the framing element, the at least one port configured to expose at least a portion of the at least one sensor element to an ambient environment; and a thin layer disposed in the at least one port. | 04-17-2014 |
20140106264 | PHOTOLITHOGRAPHY MASK, PHOTOLITHOGRAPHY MASK ARRANGEMENT, AND METHOD FOR EXPOSING A WAFER - A photolithography mask according to an embodiment may include: a mask substrate, the mask substrate having a three-dimensional pattern located and dimensioned to at least partially receive an inverse three-dimensional pattern of a wafer to be exposed using the photolithography mask. | 04-17-2014 |
20140310671 | Electrical Measurement Based Circuit Wiring Layout Modification Method and System - The capacitance or inductance of electrical circuits is adjusted by measuring inductance or capacitance values of passive components fabricated on a first substrate, storing individual associations between the passive components and the respective measured values of the passive components, and determining electrical connections for the passive components based on the stored individual associations between the passive components and the respective measured values of the passive components. A corresponding system includes a tester operable to measure inductance or capacitance values of the passive components fabricated on the first substrate, a storage system operable to store the individual associations between the passive components and the respective measured values of the passive components, and a processing circuit operable to determine the electrical connections for the passive components based on the stored individual associations between the passive components and the respective measured values of the passive components. | 10-16-2014 |
20150017801 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME - One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a substrate; forming a dielectric layer over the substrate; forming a first opening and a second opening at least partially simultaneously through the dielectric layer over the substrate; and forming a third opening through the bottom surface of the first opening and into at least a portion of the substrate. | 01-15-2015 |