Patent application number | Description | Published |
20100308415 | ANALOGUE THIN-OXIDE MOSFET - A dual gate oxide CMOS technology providing three types of transistor; a thin oxide device, a thick oxide device, and a thin oxide device using the implant type of the thick oxide device for providing improved analogue performance. | 12-09-2010 |
20110156157 | ONE-TIME PROGRAMMABLE CHARGE-TRAPPING NON-VOLATILE MEMORY DEVICE - A one-time programmable (OTP) charge-trapping non-volatile memory (NVM) device is described. In an embodiment, an OTP transistor is formed using a thick gate oxide typically used in producing an I/O MOS transistor and source/drain extensions which are highly doped, shallow and include pocket implants and which are typically used in producing a CORE thin-oxide MOS transistor. In an optimization, the OTP transistor may be formed with two narrow active areas instead of one wider active area. This provides increased performance compared to a device with a wider active area and reduced variability compared to a device with one narrow active area. In another embodiment, a dual gate oxide CMOS technology provides three types of transistor; a thin oxide device, a thick oxide device, and a thick oxide device using the implant type of the thin oxide device for providing an OTP charge-trapping NVM device. | 06-30-2011 |
20110199715 | IMPROVED METAL-ON-METAL CAPACITOR WITH DIAGONAL FEEDLINE - A design for an improved metal-on-metal capacitor design is described. The design includes a substantially diagonal feedline ( | 08-18-2011 |
20110241126 | RF CMOS TRANSISTOR DESIGN - An improved RF CMOS transistor design is described. Local, narrow interconnect lines, which are located substantially above the active area of the transistor, are each connected to either a source terminal or a drain terminal. The source and the drain terminal are arranged orthogonally to the local interconnect lines and each terminal is significantly wider than a local interconnect line. In an example, the local interconnect lines are formed in a first metal layer and the source and drain terminals are formed in one or more subsequent metal layers. | 10-06-2011 |
20110241182 | DIE SEAL RING - An improved die seal ring is described which includes at least one break. In the region of the break in the die seal ring, the doping is modified so that the impedance of the electrical path across the break through the substrate is increased. Offsets in the break may also be used and the offset may be within a break in a track and/or between breaks in different tracks, where the die seal ring includes more than one track. | 10-06-2011 |
20110266626 | GATE DEPLETION DRAIN EXTENDED MOS TRANSISTOR - A drain extended MOS transistor configured to operate in a gate-depletion regime. Devices comprising such transistors are described together with fabrication processes for such devices and transistors. | 11-03-2011 |
20120248512 | ON-GATE CONTACTS IN A MOS DEVICE - A MOS device, ( | 10-04-2012 |
20120314508 | CONTROL CIRCUITRY FOR MEMORY CELLS - Control circuitry for memory cells is described. In an embodiment, a breakdown detection circuit is described which is arranged to detect abnormally high currents indicative of a defective cell during programming of a memory cell through monitoring the impedance level at a terminal in the breakdown detection circuit. The breakdown detection circuit is connected between the device being programmed and ground and comprises three transistors, at least one of which is capable of withstanding the programming voltage in case of breakdown. Other embodiments describe a flag bit cell design, a memory array and methods of reading and writing from/to that array, and circuitry for biasing a memory word-line for both read and write operations. The embodiments may be used separately or in a combination. | 12-13-2012 |
20130015514 | SINGLE POLY NON-VOLATILE MEMORY CELLSAANM Herberholz; RainerAACI CambridgeAACO GBAAGP Herberholz; Rainer Cambridge GB - A non-volatile memory cell that includes a semiconductor substrate; a coupling capacitor located in a first active region of the semiconductor substrate; and at a shared second active region of the semiconductor substrate, a sense transistor and a tunnelling capacitor configured in parallel with the gate of the sense transistor. The coupling capacitor, sense transistor and tunnelling capacitor share a common floating gate electrode and the sense transistor includes source and drain regions arranged such that the tunnelling capacitor is defined by an overlap between the floating gate electrode and the drain region of the sense transistor. Word-line contacts may be to a separate active area from the coupling capacitor. This and/or other features can help to reduce Frenkel-Poole conduction. | 01-17-2013 |
20140027862 | RF CMOS TRANSISTOR DESIGN - An improved RF CMOS transistor design is described. Local, narrow interconnect lines, which are located substantially above the active area of the transistor, are each connected to either a source terminal or a drain terminal. The source and the drain terminal are arranged orthogonally to the local interconnect lines and each terminal is significantly wider than a local interconnect line, in an example, the local interconnect lines are formed in a first metal layer and the source and drain terminals are formed in one or more subsequent metal layers. | 01-30-2014 |
20150044838 | GATE DEPLETION DRAIN EXTENDED MOS TRANSISTOR - A drain extended MOS transistor configured to operate in a gate-depletion regime. Devices comprising such transistors are described together with fabrication processes for such devices and transistors. | 02-12-2015 |