Patent application number | Description | Published |
20110308242 | COMMAND BASED METHOD FOR ALLOCATING FLUID FLOW FROM A PLURALITY OF PUMPS TO MULTIPLE HYDRAULIC FUNCTIONS - Fluid from two pumps is allocated to a plurality of hydraulic actuators based on a plurality of flow commands, each specifying a desired amount of flow to be applied to a different hydraulic actuator. For a given hydraulic actuator, the allocation involves (1) determining an apportionment of the desired amount of flow, if no other hydraulic actuator is active, and (2) altering the apportionment in response to all the plurality of flow commands, and (3) using the altered apportionment to determine a first amount of the flow for one pump to provide and a second amount of the flow for the other pump to provide. The process is repeated for all the hydraulic actuators. Supply valves for each hydraulic actuator are controlled by the associated first and second amounts and each pump is controlled in response to either the first or second amounts for all the hydraulic actuators. | 12-22-2011 |
20120233996 | SYSTEM FOR ALLOCATING FLUID FROM MULTIPLE PUMPS TO A PLURALITY OF HYDRAULIC FUNCTIONS ON A PRIORITY BASIS - A valve assembly has a flow summation node coupled to a displacement control port of the first pump. Each valve in the assembly has a variable metering orifice controlling flow from an inlet to a hydraulic actuator and has a variable source orifice conveying fluid from a supply conduit to a flow summation node. The source orifice enlarges as the metering orifice shrinks. Each valve includes a variable bypass orifice and the bypass orifices of all the control valves are connected in series forming a bypass passage between a bypass node and a tank. The bypass node is coupled to the flow summation node and receives fluid from a second pump. At each valve, a source check valve conveys fluid from the supply conduit to the inlet and a bypass supply check valve conveys fluid from the bypass passage to the inlet. | 09-20-2012 |
20130160443 | HYDRAULIC SYSTEM WITH FLUID FLOW SUMMATION CONTROL OF A VARIABLE DISPLACEMENT PUMP AND PRIORITY ALLOCATION OF FLUID FLOW - A system has a variable displacement pump that supplies pressurized fluid to power a plurality of hydraulic functions. Each hydraulic function has a control valve with a variable source orifice controlling fluid flow between the pump and a flow summation node, and a variable metering orifice controlling fluid flow between the flow summation node and a hydraulic actuator. Variable bypass orifices in the control valves are connected in series between the flow summation node and a tank. As the metering orifice in a control valve enlarges, the source orifice enlarges and the bypass orifice shrinks. This alters pressure at the flow summation node, which is used to control the output of the pump. Components are provided to give selected hydraulic functions different levels of priority with respect to consuming fluid flow from the pump. | 06-27-2013 |
20140116038 | HYDRAULIC SYSTEM WITH OPEN LOOP ELECTROHYDRAULIC PRESSURE COMPENSATION - A hydraulic system has a pump that furnishes pressurized fluid to a supply node connected to a plurality of functions. Each function includes hydraulic actuator and a control valve assembly through which fluid flows both from the supply node to the hydraulic actuator and from the hydraulic actuator to a return line. A control method involves receiving a plurality of commands, each designating desired operation of a function. Each command is separately used to derive a flow value designating an amount of flow for the respective function, a load value indicating a load magnitude related to the respective function, and a pressure value denoting a supply pressure for the respective function. Then, the control valve assembly for each given hydraulic function is operated in response to the flow and load values for that function and in response to the pressure value that is greatest among the plurality of functions. | 05-01-2014 |
Patent application number | Description | Published |
20080256150 | Three-path fused multiply-adder circuit - A three-path floating-point fused multiply-adder is disclosed. The fused multiply-adder is for the single instruction execution of (A×B)+C. The three-path fused multiply-adder is based on a dual-path adder and reduces latency significantly by operating on case data in parallel and by reducing component bit size. The fused multiply-adder is a common serial fused multiply-adder that reuses floating-point adder (FPA) and floating-point multiplier (FPM) hardware, allowing single adds, single multiplies, and fused multiply-adds to execute at maximum speed. | 10-16-2008 |
20080256161 | Bridge Fused Multiply-Adder Circuit - A bridge fused multiply-adder is disclosed. The fused multiply-adder is for the single instruction execution of (A×B)+C. The bridge fused multiply-add unit adds this functionality to existing floating-point co-processor units by including a fused multiply-add hardware “bridge” between an existing floating-point adder and a floating-point multiplier unit. This fused multiply-add functionality is added to existing two-operand architecture designs without degrading the performance or parallel pipe execution of floating-point adder and floating-point multiplier instructions. | 10-16-2008 |
20120119816 | VARIABLE-WIDTH POWER GATING MODULE - A semiconductor device includes a primary voltage rail, a secondary voltage rail, a plurality of transistors coupled between the primary and secondary voltage rails, and control logic operable to enable a first subset of the plurality of transistors to couple the primary voltage rail to the secondary voltage rail. During a steady state condition, the first subset comprises less than all of the plurality of transistors. | 05-17-2012 |
20140176190 | COARSE GATING OF CLOCK TREE ELEMENTS - Methods relating to distribution of a clock signal to logic devices of an integrated circuit. The method includes controlling, by a logic element, the distribution of a clock signal by a dock gater and distributing the clock signal by the clock gater to at least one first logic device, wherein the logic element allows the first clock gater to distribute the clock signal only when at least one first logic device requires the clock signal. An integrated circuit configured to perform such a method. Fabrication of such an integrated circuit. | 06-26-2014 |
20140237312 | Scan Warmup Scheme for Mitigating DI/DT During Scan Test - We report methods relating to scan warmup of integrated circuit devices. One such method may comprise loading a scan test stimulus to and unloading a scan test response from a first set of logic elements of an integrated circuit device at a scan clock first frequency equal to a test clock frequency; adjusting the scan clock from the first frequency to a second frequency by a scan warmup unit, wherein the scan clock second frequency is equal to a system clock frequency; and capturing the scan test response by a shift logic at the scan clock second frequency. We also report processors containing components configured to implement the method, and fabrication of such processors. The methods and their implementation may reduce di/dt events otherwise commonly occurring when testing logic elements of integrated circuit devices. | 08-21-2014 |