Patent application number | Description | Published |
20120142121 | HYDROCHLORIC ACID ETCH AND LOW TEMPERATURE EPITAXY IN A SINGLE CHAMBER FOR RAISED SOURCE-DRAIN FABRICATION - A raised source-drain structure is formed using a process wherein a semiconductor structure is received in a process chamber that is adapted to support both an etching process and an epitaxial growth process. This semiconductor structure includes a source region and a drain region, wherein the source and drain regions each include a damaged surface layer. The process chamber is controlled to set a desired atmosphere and set a desired temperature. At the desired atmosphere and temperature, the etching process of process chamber is used to remove the damaged surface layers from the source and drain regions and expose an interface surface. Without releasing the desired atmosphere and while maintaining the desired temperature, the epitaxial growth process of the process chamber is used to grow, from the exposed interface surface, a raised region above each of the source and drain regions. | 06-07-2012 |
20120146175 | INSULATING REGION FOR A SEMICONDUCTOR SUBSTRATE - An insulating region for a semiconductor wafer and a method of forming same. The insulating region can include a tri-layer structure of silicon oxide, boron nitride and silicon oxide. The insulating region may be used to insulate a semiconductor device layer from an underlying bulk semiconductor substrate. The insulating region can be formed by coating the sides of a very thin cavity with silicon oxide, and filling the remainder of the cavity between the silicon oxide regions with boron nitride. | 06-14-2012 |
20120156847 | LAYER FORMATION WITH REDUCED CHANNEL LOSS - Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process. | 06-21-2012 |
20130193494 | TRANSISTOR WITH COUNTER-ELECTRODE CONNECTION AMALGAMATED WITH THE SOURCE/DRAIN CONTACT - The field effect device includes an active area made from semi-conducting material and a gate electrode separated from the active area by a dielectric gate material. A counter-electrode is separated from the active area by a layer of electrically insulating material. Two source/drain contacts are arranged on the active area on each side of the gate electrode. One of the source/drain contacts is made from a single material, overspills from the active area and connects the active area with the counter-electrode. The counter-electrode contact is delineated by a closed peripheral insulating pattern. | 08-01-2013 |
20130193514 | METHOD TO ENABLE THE FORMATION OF SILICON GERMANIUM CHANNEL OF FDSOI DEVICES FOR PFET THRESHOLD VOLTAGE ENGINEERING - An SOI substrate has a first region isolated from a second region. An SiGe layer is deposited on top of the SOI substrate in the second region. The substrate is subjected to a thermal oxidation process which drives in Ge from the SiGe layer to form an SiGeOI structure in the second region and an overlying oxide layer. If the SOI substrate is exposed in the first region, the thermal oxidation process further produces an oxide layer overlying the first region. The oxide layer(s) is(are) removed to expose an Si channel layer in the first region and an SiGe channel layer in the second region. Transistor gate stacks are formed over each of the Si channel layer and SiGe channel layer. Raised source and drain regions are formed from the Si channel layer and SiGe channel layer adjacent the transistor gate stacks. | 08-01-2013 |
20130277747 | TRANSISTOR HAVING A STRESSED BODY - An embodiment of a transistor includes a body and a semiconductor region configured to stress a portion of the body. For example, stressing a channel of the transistor may increase the mobility of carriers in the channel, and thus may reduce the “on” resistance of the transistor. For example, the substrate, source/drain regions, or both the substrate and source/drain regions of a PFET may be doped to compressively stress the channel so as to increase the mobility of holes in the channel. Or, the substrate, source/drain regions, or both the substrate and source/drain regions of an NFET may be doped to tensile stress the channel so as to increase the mobility of electrons in the channel. | 10-24-2013 |
20130334651 | DUAL SHALLOW TRENCH ISOLATION LINER FOR PREVENTING ELECTRICAL SHORTS - A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate. | 12-19-2013 |
20140054698 | ELECTRONIC DEVICE INCLUDING SHALLOW TRENCH ISOLATION (STI) REGIONS WITH BOTTOM NITRIDE LINER AND UPPER OXIDE LINER AND RELATED METHODS - An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one STI region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include a nitride layer lining a bottom portion of the sidewall surface, an oxide layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers. | 02-27-2014 |
20140054699 | ELECTRONIC DEVICE INCLUDING SHALLOW TRENCH ISOLATION (STI) REGIONS WITH BOTTOM OXIDE LINER AND UPPER NITRIDE LINER AND RELATED METHODS - An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one shallow trench isolation (STI) region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include an oxide layer lining a bottom portion of the sidewall surface, a nitride layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers. | 02-27-2014 |
20140054706 | MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSIDE SURFACES OF OUTERMOST FINS AND RELATED METHODS - A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof. | 02-27-2014 |
20140054715 | SEMICONDUCTOR DEVICE WITH AN INCLINED SOURCE/DRAIN AND ASSOCIATED METHODS - A semiconductor device includes a semiconductor substrate having a channel region therein, a gate structure above the channel region, and source and drain regions on opposite sides of the gate structure. A respective contact is on each of the source and drain regions. At least one of the source and drain regions has an inclined upper contact surface with the respective contact. The inclined upper contact surface has at least a 50% greater area than would a corresponding flat contact surface. | 02-27-2014 |
20140084372 | DUAL SHALLOW TRENCH ISOLATION LINER FOR PREVENTING ELECTRICAL SHORTS - A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate. | 03-27-2014 |
20140099769 | METHOD TO PROTECT AGAINST CONTACT RELATED SHORTS ON UTBB - Isolation trenches are etched through an active silicon layer overlying a buried oxide on a substrate into the substrate, and through any pad dielectric(s) on the active silicon layer. Lateral epitaxial growth of the active silicon layer forms protrusions into the isolation trenches to a lateral distance of at least about 5 nanometers, and portions of the isolation trenches around the protrusions are filled with dielectric. Raised source/drain regions are formed on portions of the active silicon layer including a dielectric. As a result, misaligned contacts passing around edges of the raised source/drain regions remain spaced apart from sidewalls of the substrate in the isolation trenches. | 04-10-2014 |
20140099773 | DUAL SHALLOW TRENCH ISOLATION LINER FOR PREVENTING ELECTRICAL SHORTS - A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate. | 04-10-2014 |
20140151759 | FACET-FREE STRAINED SILICON TRANSISTOR - The presence of a facet or a void in an epitaxially grown crystal indicates that crystal growth has been interrupted by defects or by certain material boundaries. Faceting can be suppressed during epitaxial growth of silicon compounds that form source and drain regions of strained silicon transistors. It has been observed that faceting can occur when epitaxial layers of certain silicon compounds are grown adjacent to an oxide boundary, but faceting does not occur when the epitaxial layer is grown adjacent to a silicon boundary or adjacent to a nitride boundary. Because epitaxial growth of silicon compounds is often necessary in the vicinity of isolation trenches that are filled with oxide, techniques for suppression of faceting in these areas are of particular interest. One such technique, presented herein, is to line the isolation trenches with SiN to provide a barrier between the oxide and the region in which epitaxial growth is intended. | 06-05-2014 |
20140170834 | METHOD FOR MANUFACTURING A HYBRID SOI/BULK SEMICONDUCTOR WAFER - A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings. | 06-19-2014 |
20140210010 | METHOD TO FORM FINFET/TRIGATE DEVICES ON BULK SEMICONDUCTOR WAFERS - A method for fabricating a finFET device having an insulating layer that insulates the fin from a substrate is described. The insulating layer can prevent leakage current that would otherwise flow through bulk semiconductor material in the substrate. The structure may be fabricated starting with a bulk semiconductor substrate, without the need for a semiconductor-on-insulator substrate. Fin structures may be formed by epitaxial growth, which can improve the uniformity of fin heights in the devices. | 07-31-2014 |
20140239395 | CONTACT RESISTANCE REDUCTION IN FINFETS - A method for forming contacts in a semiconductor device includes forming a plurality of substantially parallel semiconductor fins on a dielectric layer of a substrate having a gate structure formed transversely to a longitudinal axis of the fins. The fins are merged by epitaxially growing a crystalline material between the fins. A field dielectric layer is deposited over the fins and the crystalline material. Trenches that run transversely to the longitudinal axis of the fins are formed to expose the fins in the trenches. An interface layer is formed over portions of the fins exposed in the trenches. Contact lines are formed in the trenches that contact a top surface of the interface layer on the fins and at least a portion of side surfaces of the interface layer on the fins. | 08-28-2014 |
20140239415 | STRESS MEMORIZATION IN RMG FINFETS - Transistors with memorized stress and methods for making such transistors. The methods include forming a transistor structure having a channel region, a source and drain region, and a gate dielectric; depositing a stressor over the channel region of the transistor structure, wherein the stressor provides a stress to the channel region; removing the stressor metal after the stress is memorized within the channel region; and depositing a work function metal over the channel region of the transistor structure, where the work function metal applies less stress to the channel region than the stress applied by the stressor. A transistor with memorized stress includes a source and drain region on a substrate; a stress-memorized channel region on the substrate that retains an externally applied stress; and a gate structure including a work function gate metal that applies less stress to the stress-memorized channel region than the externally applied stress. | 08-28-2014 |
20140291749 | MEMORY DEVICE HAVING MULTIPLE DIELECTRIC GATE STACKS AND RELATED METHODS - A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack. The gate stack may include a first dielectric layer over the channel region, a first diffusion barrier layer over the first dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second dielectric layer over the first electrically conductive layer, a second diffusion barrier layer over the second dielectric layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer. | 10-02-2014 |
20140291750 | MEMORY DEVICE HAVING MULTIPLE DIELECTRIC GATE STACKS WITH FIRST AND SECOND DIELECTRIC LAYERS AND RELATED METHODS - A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack having a first dielectric layer over the channel region, a second dielectric layer over the first dielectric layer, a first diffusion barrier layer over the second dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second diffusion barrier layer over the first electrically conductive layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer. | 10-02-2014 |
20140302661 | CONTACT ISOLATION SCHEME FOR THIN BURIED OXIDE SUBSTRATE DEVICES - A method of forming a semiconductor-on-insulator (SOI) device includes defining a shallow trench isolation (STI) structure in an SOI substrate, the SOI substrate including a bulk layer, a buried insulator (BOX) layer over the bulk layer, and an SOI layer over the BOX layer; forming a doped region in a portion of the bulk layer corresponding to a lower location of the STI structure, the doped region extending laterally into the bulk layer beneath the BOX layer; selectively etching the doped region of the bulk layer with respect to undoped regions of the bulk layer such that the lower location of the STI structure undercuts the BOX layer; and filling the STI structure with an insulator fill material. | 10-09-2014 |
20140312423 | SIMPLIFIED MULTI-THRESHOLD VOLTAGE SCHEME FOR FULLY DEPLETED SOI MOSFETS - A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided. | 10-23-2014 |
20140312461 | DEFECTIVE P-N JUNCTION FOR BACKGATED FULLY DEPLETED SILICON ON INSULATOR MOSFET - Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased. | 10-23-2014 |
20140345517 | METHOD FOR THE FORMATION OF NANO-SCALE ON-CHIP OPTICAL WAVEGUIDE STRUCTURES - A strip of sacrificial semiconductor material is formed on top of a non-sacrificial semiconductor material substrate layer. A conformal layer of the non-sacrificial semiconductor material is epitaxially grown to cover the substrate layer and the strip of sacrificial semiconductor material. An etch is performed to selectively remove the strip of sacrificial semiconductor material and leave a hollow channel surrounded by the conformal layer and the substrate layer. Using an anneal, the conformal layer and the substrate layer are reflowed to produce an optical waveguide structure including the hollow channel. | 11-27-2014 |
20140353717 | SILICON-ON-NOTHING TRANSISTOR SEMICONDUCTOR STRUCTURE WITH CHANNEL EPITAXIAL SILICON REGION - An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon region disposed on a substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and growing a raised epitaxial source and drain from the substrate, the raised epitaxial source and drain in contact with the epitaxial silicon region and the gate stack structure. For a SRAM device, further: removing an epitaxial layer in contact with the silicon substrate and the raised source and drain and to which the epitaxial silicon region is coupled leaving a space above the silicon substrate and under the raised epitaxial source and drain; and filling the space with an insulating layer and isolating the raised epitaxial source and drain and a channel of the transistor from the silicon substrate. | 12-04-2014 |
20140353718 | SILICON-ON-NOTHING TRANSISTOR SEMICONDUCTOR STRUCTURE WITH CHANNEL EPITAXIAL SILICON-GERMANIUM REGION - An improved transistor with channel epitaxial silicon and methods for fabrication thereof. In one aspect, a method for fabricating a transistor includes: forming a gate stack structure on an epitaxial silicon region, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; encapsulating the epitaxial silicon region under the gate stack structure with sacrificial spacers formed on both sides of the gate stack structure and the epitaxial silicon region; forming a channel of the transistor having a width dimension that approximates that of the epitaxial silicon region and the gate stack structure, the epitaxial silicon region and the gate stack structure formed on the channel of the transistor; removing the sacrificial spacers; and growing a raised epitaxial source and drain from the silicon substrate, with portions of the raised epitaxial source and drain in contact with the epitaxial silicon region. | 12-04-2014 |
20140353753 | FIN FIELD EFFECT TRANSISTOR DEVICE WITH REDUCED OVERLAP CAPACITANCE AND ENHANCED MECHANICAL STABILITY - Improved fin field effect transistor (FinFET) devices and methods for fabrication thereof. In one aspect, a method for fabricating a FinFET device comprises: a silicon substrate on which a silicon epitaxial layer is grown is provided. Sacrificial structures on the substrate are formed from the epitaxial layer. A blanket silicon layer is formed over the sacrificial structures and exposed substrate portions, the blanket silicon layer having upper and lower portions of uniform thickness and intermediate portions interposed between the upper and lower portions of non-uniform thickness and having an angle of formation. An array of semiconducting fins is formed from the blanket silicon layer and a non-conformal layer formed over the blanket layer. The sacrificial structures are removed and the resulting void filled with isolation structures under the channel regions. Source and drain are formed in the source/drain regions during a fin merge of the FinFET. | 12-04-2014 |
20140353760 | METHOD TO CO-INTEGRATE SiGe AND Si CHANNELS FOR FINFET DEVICES - A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level. | 12-04-2014 |
20140353767 | METHOD FOR THE FORMATION OF FIN STRUCTURES FOR FINFET DEVICES - On a first semiconductor material substrate, an overlying sacrificial layer formed of a second semiconductor material is deposited. In a first region, a first semiconductor material region is formed over the sacrificial layer. In a second region, a second semiconductor material region is formed over the sacrificial layer. The first semiconductor material region is patterned to define a first FinFET fin. The second semiconductor material region is patterned to define a second FinFET fin. The fins are each covered with a cap and sidewall spacer. The sacrificial layer formed of the second semiconductor material is then selectively removed to form an opening below each of the first and second FinFET fins (with those fins being supported by the sidewall spacers). The openings below each of the fins are then filled with a dielectric material that serves to isolate the semiconductive materials of the fins from the substrate. | 12-04-2014 |
20140357039 | METHOD FOR THE FORMATION OF A PROTECTIVE DUAL LINER FOR A SHALLOW TRENCH ISOLATION STRUCTURE - On a substrate formed of a first semiconductor layer, an insulating layer and a second semiconductor layer, a silicon oxide pad layer and a silicon nitride pad layer are deposited and patterned to define a mask. The mask is used to open a trench through the first semiconductor layer and insulating layer and into the second semiconductor layer. A dual liner of silicon dioxide and silicon nitride is conformally deposited within the trench. The trench is filled with silicon dioxide. A hydrofluoric acid etch removes the silicon nitride pad layer along with a portion of the conformal silicon nitride liner. A hot phosphoric acid etch removes the silicon oxide pad layer, a portion of the silicon oxide filling the trench and a portion of the conformal silicon nitride liner. The dual liner protects against substrate etch through at an edge of the trench between the first and second semiconductor layers. | 12-04-2014 |
20140357060 | METHOD FOR THE FORMATION OF FIN STRUCTURES FOR FINFET DEVICES - A SOI substrate layer formed of a silicon semiconductor material includes adjacent first and second regions. A portion of the silicon substrate layer in the second region is removed such that the second region retains a bottom portion made of the silicon semiconductor material. An epitaxial growth of a silicon-germanium semiconductor material is made to cover the bottom portion. Germanium is then driven from the epitaxially grown silicon-germanium material into the bottom portion to convert the bottom portion to silicon-germanium. Further silicon-germanium growth is performed to define a silicon-germanium region in the second region adjacent the silicon region in the first region. The silicon region is patterned to define a first fin structure of a FinFET of a first (for example, n-channel) conductivity type. The silicon-germanium region is also patterned to define a second fin structure of a FinFET of a second (for example, p-channel) conductivity type. | 12-04-2014 |